IP Library Granted Patent US 7,002,495
Granted Patent B1
US 7,002,495 · App. 11/031,609 · Granted Feb 21, 2006

Analog to digital converter with distortion correction

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Quick Facts
Patent No.
US 7,002,495
App. No.
11/031,609
Granted
Feb 21, 2006
Kind
B1
Abstract

A method of correcting for output distortion of an analog to digital converter (ADC) is disclosed. The method comprises estimating the output distortion and providing an estimated distortion. The method further comprises combining an output of the ADC with the estimated distortion to compensate for the output distortion and training a calibration module.

Claims (38)

1. A method of correcting for output distortion of an analog to digital converter (ADC) comprising:

estimating the output distortion;

providing an estimated distortion;

combining an output of the ADC with the estimated distortion to compensate for the output distortion; and

training a calibration module.

2. A method as recited in claim 1 , wherein training the calibration module includes feeding back an error adaptation signal to adapt the calibration module.

3. A method as recited in claim 1 , wherein:

the calibration module comprises a nonlinear filter; and

training the calibration module includes applying a signal to the calibration module and feeding back an error adaptation signal to adapt a coefficient of the nonlinear filter.

4. A method as recited in claim 1 , wherein training includes:

selecting a most significant bit output of the ADC;

applying the selected most significant bit output to the calibration module; and adapting the calibration module.

5. A method as recited in claim 1 , wherein training includes:

selecting a most significant bit output of the ADC;

applying the selected most significant bit output to the calibration module; and

adapting the calibration module to reduce the interference of the selected most significant bit output on a least significant output bit output of the ADC.

6. A method as recited in claim 1 , wherein training a calibration module includes using a digital to analog converter.

7. A method as recited in claim 1 , wherein training a calibration module includes using a dynamic element matching digital to analog converter.

8. A compensating module for correcting output distortion of an analog to digital converter (ADC), comprising:

a calibration module configured to estimate the output distortion wherein the calibration module is trainable; and

a combiner configured to combine an output of the ADC with the estimated distortion to compensate the output distortion.

9. A distortion correcting analog to digital converter (ADC) comprising:

a digitizing circuit having an output distortion;

a calibration module configured to estimate the output distortion wherein the calibration module is configurable to be trained; and

a combiner configured to combine an output of the ADC with the estimated distortion to compensate the output distortion.

10. A distortion correcting ADC as recited in claim 1 , wherein the training includes feeding back an error adaptation signal to adapt the calibration module.

11. A distortion correcting ADC as recited in claim 9 , wherein:

the training includes:

selecting a most significant bit output of the ADC;

applying the selected most significant bit output to the calibration module; and adapting the calibration module.

12. A distortion correcting ADC as recited in claim 9 , wherein:

the training includes:

selecting a most significant bit output of the ADC;

applying the selected most significant bit output to the calibration module; and

adapting the calibration module to reduce the interference of the selected most significant bit output on a least significant output bit output of the ADC.

13. A distortion correcting ADC as recited in claim 9 , training uses a uniform noise source.

14. A distortion correcting ADC as recited in claim 9 , training uses a digital to analog converter.

15. A distortion correcting ADC as recited in claim 9 , training uses a dynamic element matching digital to analog converter.

Assignments (3)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →