RF circuits including transistors having strained material layers
View Patent ↗Circuits for processing radio frequency (“RF”) and microwave signals are fabricated using field effect transistors (“FETs”) that have one or more strained channel layers disposed on one or more planarized substrate layers. FETs having such a configuration exhibit improved values for, for example, transconductance and noise figure. RF circuits such as, for example, voltage controlled oscillators (“VCOs”), low noise amplifiers (“LNAs”), and phase locked loops (“PLLs”) built using these FETs also exhibit enhanced performance.
1. A circuit for processing an RF signal comprising at least one FET to which the RF signal is applied, the at least one FET comprising:
a semiconductor substrate including at least one planarized layer;
a channel region including at least one strained channel layer disposed on the at least one planarized layer thereby defining an interface therebetween, the at least one strained channel layer having a distal zone away from the interface, wherein the substrate, the interface, and the at least one strained channel layer are characterized at least in part by an impurity gradient having a value substantially equal to zero in the distal zone; and
a gate electrode.
2. The circuit of claim 1 wherein the substrate comprises Si.
3. The circuit of claim 1 wherein the substrate comprises SiGe.
4. The circuit of claim 1 wherein the at least one planarized layer comprises relaxed SiGe disposed on compositionally graded SiGe.
5. The circuit of claim 1 wherein the at least one planarized layer comprises relaxed SiGe disposed on Si.
6. The circuit of claim 1 wherein the substrate comprises a buried insulating layer.
7. The circuit of claim 1 wherein the at least one strained channel layer comprises Si.
8. The circuit of claim 1 wherein the at least one strained channel layer comprises Ge.
9. The circuit of claim 1 wherein the at least one strained channel layer comprises SiGe.
10. The circuit of claim 1 wherein the channel region comprises n-type conductivity.
11. The circuit of claim 1 wherein the channel region comprises p-type conductivity.
12. The circuit of claim 1 wherein a gate dielectric is disposed substantially between the gate electrode and the channel region.
13. The circuit of claim 1 wherein the FET comprises an interdigitated structure.
14. The circuit of claim 1 wherein an excess carrier supply region is disposed substantially adjacent to the channel region.
15. The circuit of claim 14 wherein the excess carrier supply region is formed at least in part by implantation of at least one impurity.
16. The circuit of claim 1 wherein the circuit comprises a voltage controlled oscillator.
17. The circuit of claim 1 wherein the circuit comprises a low noise amplifier.
18. The circuit of claim 1 wherein the circuit comprises a phase locked loop.
19. The circuit of claim 1 wherein the distal zone comprises at least about fifty Angstroms of the at least one strained channel layer.