Flexible SDRAM clocking (MS-DLL)
View Patent ↗A delay lock loop for use in meeting SDRAM timing requirements, wherein a timing relationship between data generated by a computer chip and a clock in said DRAM is fully programmable, and wherein said delay lock loop is digitally implemented. The delay lock loop includes a first delay chain to measure a number of delay taps in a single clock cycle of the clock of the SDRAM and a second delay chain to delay the clock of the SDRAM. The second delay chain is matched to the first delay chain.
1. A delay lock loop for use in meeting SDRAM timing requirements, wherein a timing relationship between data generated by a computer chip and a clock in said SDRAM is fully programmable, and wherein said delay lock loop is digitally implemented, wherein said digital implementation comprises:
a first delay chain to measure a number of delay taps in a single clock cycle of the clock of the SDRAM; and
a second delay chain to delay the clock of the SDRAM, the second delay chain matched to the first delay chain.
2. The delay lock loop according to claim 1 , wherein said programmable timing relationship is specified as a percent offset from ideal, wherein ideal is defined as when said data changes at the same instant as a rising edge of said clock.
3. The delay lock loop of claim 1 , wherein the first delay chain is continually calibrated to account for changes in temperature and voltage during operation of a circuit.
4. The delay lock loop of claim 1 , wherein the number of delay taps is multiplied by a phase percentage to give a target number of delay elements by which the second delay chain is to delay the clock.
5. A method of meeting timing requirements between a clock in SDRAM and data generated by a computer chip, the method comprising:
implementing a delay lock loop, wherein:
a timing relationship between said clock and said data is fully programmable in said delay lock loop; and
the delay lock loop is digital, wherein the delay lock loop comprises:
a first delay chain to measure the number of delay taps in a single clock cycle of the clock of the SDRAM; and
a second delay chain to delay the clock of the SDRAM, the second delay chain matched to the first delay chain.
6. The method according to claim 5 , wherein said programmable timing relationship is specified as a percent offset from ideal, wherein ideal is defined as when said data changes at the same instant as a rising edge of said clock.
7. The method of claim 5 , further comprising:
continually calibrating the number of delay taps to account for changes in temperature and voltage during operation.
8. The method of claim 7 , further comprising:
multiplying the number of delay taps by a phase percentage to produce a target number of delay elements; and
delaying the clock of the SDRAM by the target number of delay elements.
9. The delay lock loop for use in a synchronous dynamic random access memory (SDRAM) device; the delay lock loop comprising:
a first delay chain to measure a number of delay taps in a single clock cycle of an SDRAM clock; and
a second delay chain responsive to the first delay chain to delay the SDRAM clock by a target number of delay elements derived from the number of delay taps;
wherein the delay lock loop is digital; and
wherein a timing relationship between data generated by a computer chip and a clock signal of the SDRAM clock is fully programmable.
10. The delay lock loop of claim 9 , wherein the timing relationship comprises a phase adjustment related to a difference between a data change and an edge of the SDRAM clock.
11. The delay lock loop of claim 10 , wherein the edge of the SDRAM clock comprises a rising edge.
12. The delay lock loop of claim 10 , wherein the phase adjustment is programmable.
13. The delay lock loop of claim 9 , wherein the first delay chain is calibrated continually to account for changes in temperature and voltage during operation.