Generic ink jet head fire logic
View Patent ↗An inkjet firing architecture for use in association with a device utilizing an ink jet head. The inkjet firing architecture includes a fire synchronization block including an N-entry delay line, at least one vector sequencing block, and a vector compositing block. The N-entry delay line is operable to simultaneously delay multiple incoming external events for varying periods of time prior to passing each of the events to one of M event sub-dividing stages and provide a fire synchronization block output that is related at least in part to the delayed incoming external events. Each of the M event sub-dividing stages emits a programmable series of sub-events, each of the sub-events being separated in time by a sub-event interval. Each programmable series of sub-events ends with an independent Mth level sub-event that is passed along as the fire synchronization block output to the at least one vector sequencing block.
1. An inkjet firing architecture for use in association with a device utilizing an ink jet head, the architecture comprising:
a fire synchronization block comprising an N-entry delay line operable to simultaneously delay multiple incoming external events for varying periods of time prior to passing each of the events to one of M event sub-dividing stages and to provide a fire synchronization block output that is related at least in part to the delayed incoming external events, wherein each of the M event sub-dividing stages emits a programmable series of sub-events, each of the sub-events being separated in time by a sub-event interval;
at least one vector sequencing block operable to receive the fire synchronization block output and to provide at least one of a control signal for the ink jet head and data related to selected nozzles to be fired as a vector sequencing block output; and
a vector compositing block to form a composite output vector by combining output from the at least one vector sequencing block, and to provide the composite output vector to the ink jet head;
wherein each programmable series of sub-events ends with an independent Mth level sub-event that is passed along as the fire synchronization block output to the at least one vector sequencing block.
2. The inkjet firing architecture of claim 1 , wherein an exit time is calculated for each incoming external event by adding to a time of entry in the N-entry delay line a delay lock factor and a compensation factor, and wherein each incoming event is loaded into a First In First Out (FIFO) buffer, based at least in part upon a calculated exit time.
3. The inkjet firing architecture of claim 2 , wherein the delay lock factor is calculated by:
determining a time difference between a current incoming event and an immediately preceding incoming event; and
multiplying the time difference by a phase factor.
4. An inkjet firing architecture according to claim 1 wherein at least one vector sequencing block outputs a sequence of fixed bit width output vectors obtained by systematically reading from a memory.
5. An inkjet firing architecture according to claim 1 wherein the at least one vector sequencing block reads a compressed form of output vectors from a memory, decompresses the output vectors and outputs the decompressed output vectors.
6. An inkjet firing architecture according to claim 5 , wherein the memory is selected from memory resident on an SoC ASIC and memory external to the SoC ASIC.
7. The inkjet firing architecture of claim 1 , wherein a first vector sequencing block is operable to produce a first series of output vectors comprising control signals for the inkjet head, and a second vector sequencing block is operable to produce to produce a second series of output vectors comprising data that represents which nozzles to fire.
8. The inkjet firing architecture of claim 1 , wherein the composite output vector further includes vectors derived from a source selected from a control state register programmable by firmware or a pulse-width modulation circuit.
9. A computer chip comprising the ink jet firing architecture of claim 1 .
10. The computer chip of claim 9 , wherein the computer chip is a universal multifunction peripheral architecture chip.
11. The inkjet firing mechanism of claim 1 , wherein the fire synchronization block is operative to:
receive N incoming events, each incoming event separated in time from a subsequent incoming event by a corresponding incoming time interval, wherein the incoming time intervals between the N incoming events can be characterized by a first set of intervals;
from those incoming events, create Y outgoing events based at least in part on the incoming events, wherein time intervals between the Y outgoing events can be characterized by a second set of intervals.
12. The inkjet firing mechanism of claim 11 , wherein N<Y.
13. The inkjet firing mechanism of claim 11 , wherein the second set of intervals are substantially equal in value.
14. The inkjet firing mechanism of claim 1 , wherein said ink jet fire architecture comprises two vector sequencing blocks.
15. The inkjet firing mechanism of claim 14 , wherein one of the vector sequencing blocks is operative to provide one or more control signals to the ink jet head.
16. The inkjet firing mechanism of claim 14 , wherein one of the vector sequencing blocks is operative to provide data representing which nozzles to fire.
17. A print head actuation architecture for use in association with a device utilizing a print head, the architecture comprising:
a fire synchronization block comprising an N-entry delay line operable to simultaneously delay multiple incoming external events for varying periods of time prior to passing each of the events to one of M event sub-dividing stages and to provide a fire synchronization block output that is related at least in part to the delayed incoming external events, wherein each of the M event sub-dividing stages emits a programmable series of sub-events, each of the sub-events being separated in time by a sub-event interval;
at least one vector sequencing block operable to receive the fire synchronization block output and to provide a control signal for the print head as a vector sequencing block output; and
a vector compositing block to form a composite output vector by combining output from the at least one vector sequencing block, and to provide the composite output vector to the print head;
wherein each programmable series of sub-events ends with an independent Mth level sub-event that is passed along as the fire synchronization block output to the at least one vector sequencing block.
18. The print head actuation architecture of claim 17 , wherein said print head comprises an ink jet head.
19. A print head actuation architecture according to claim 17 wherein said print head comprises a thermal print head.
20. A print head actuation architecture according to claim 19 wherein said print head comprises a thermal transfer print head.
21. A print head actuation architecture according to claim 17 wherein said print head comprises a thermal transfer dye sublimation print head.