Canonical signed digit (CSD) coefficient multiplier with optimization

1. An apparatus comprising:

an address generation circuit configured to generate a series of addresses;

a lookup table configured to generate one or more coefficients in response to said addresses, each one of said coefficients having a plurality of bits;

a multiplexer circuit configured to generate one or more shifted values by multiplexing one or more operands and a plurality of arithmetically shifted versions of said operands, wherein said multiplexing is controlled by said coefficients such that each of said shifted values represents one of (i) said operands or (ii) said arithmetically shifted versions of said operands multiplied by a corresponding one of said bits; and

an output circuit configured to (i) generate one or more component values by rounding said shifted values, (ii) negate selective ones of said component values and (iii) generate an output signal by combining said component values after said negating, wherein (a) said component values are grouped as one over power of 2 components into mutually exclusive groups, (b) each one of said groups corresponds to a respective one of said bits and (c) said output signal is suitable for use in a digital filter.

2. The apparatus according to claim 1 , wherein (i) said output circuit is further configured to generate one or more signed values in response to said addresses by using a lookup register and (ii) a negative value on said signed values selects said component values to said negate.

3. The apparatus according to claim 1 , wherein:

said multiplexer circuit comprises a plurality of sub-multiplexers that generate a plurality of said shifted values in parallel; and

said output circuit comprises a plurality of rounder circuits that generate said component values in parallel, wherein the number of said sub-multiplexers and said rounders is (i) fewer than that of said bits and (ii) increased to increase an accuracy of said output signal.

4. The apparatus according to claim 1 , wherein said one or more coefficients comprise canonical signed digit (CSD) coefficients.

5. The apparatus according to claim 4 , wherein said CSD coefficients reduce an overall gate count needed to implement said apparatus.

6. The apparatus according to claim 1 , wherein said coefficients are programmable.

7. The apparatus according to claim 1 , wherein said coefficients are fixed.

8. The apparatus according to claim 1 , wherein said one over power of 2 grouping reduces a gate count of said apparatus.

9. The apparatus according to claim 1 , wherein said apparatus forms a canonical signed digit (CSD) coefficient multiplier.

10. An apparatus comprising:

means for generating a series of addresses;

means for generating one or more coefficients in response to said addresses, each one of said coefficients having a plurality of bits;

means for generating one or more shifted values by multiplexing one or more operands and a plurality of arithmetically shifted versions of said operands, wherein said multiplexing is controlled by said coefficients such that each of said shifted values represents one of (i) said operands or (ii) said arithmetically shifted versions of said operands multiplied by a corresponding one of said bits; and

means for (i) generating one or more component values by rounding said shifted values, (ii) negating selective ones of said component values, and (iii) generating an output signal by combining said component values after said negating, wherein (a) said component values are grouped as one over power of 2 components into mutually exclusive groups, (b) each one of said groups corresponds to a respective one of said bits and (c) said output signal is suitable for use in a digital filter.

11. The apparatus according to claim 10 , further comprising a lookup register means for generating one or more signed values in response to said addresses, wherein a negative value on said signed values selects said component values to said negate.

12. A method for implementing a multiplier comprising the steps of:

(A) generating a series of addresses;

(B) generating one or more coefficients from a lookup table in response to said addresses, each one of said coefficients having a plurality of bits;

(C) generating one or more shifted values by multiplexing one or more operands and a plurality of arithmetically shifted versions of said operands, wherein said multiplexing is controlled by said coefficients such that each of said shifted values represents one of (i) said operands or (ii) said arithmetically shifted versions of said operands multiplied by a corresponding one of said bits;

(D) generating one or more component values by rounding said shifted values;

(E) negating selective ones of said component values; and

(F) generating an output signal by combining said component values after said negating, wherein (i) said component values are grouped as one over power of 2 components into mutually exclusive groups, (ii) each one of said groups corresponds to a respective one of said bits and (iii) said output signal is suitable for use in a digital filter.

13. The method according to claim 12 , further comprising the step of:

generating one or more signed values in response to said addresses by using a lookup register, wherein a negative value on said signed values selects said component values to said negate.

14. The method according to claim 12 , wherein:

step (C) is implemented using a plurality of sub-multiplexers that generate a plurality of said shifted values in parallel; and

step (D) is implemented using a plurality of rounder circuits that generate said component values in parallel, wherein the number of said sub-multiplexers and said rounders is (i) fewer than that of said bits and (ii) increased to increase an accuracy of said output signal.

15. The method according to claim 12 , wherein said one or more coefficients comprise canonical signed digit (CSD) coefficients.

16. The method according to claim 15 , wherein said CSD coefficients reduce an overall gate count needed to implement said method.

17. The method according to claim 12 , wherein said coefficients are programmable.

18. The method according to claim 12 , wherein said coefficients are fixed.

19. The method according to claim 12 , wherein said one over power of 2 grouping reduces a gate count when implementing said method.

20. The method according to claim 12 , wherein said method is implemented in a canonical signed digit (CSD) coefficient multiplier.