Delay equalized Z/2Z ladder for digital to analog conversion
View Patent ↗A Z/2Z ladder network includes an R/2R ladder network having capacitors coupled across series resistors within the R/2R ladder network, wherein the capacitors are sized to substantially match delays from nodes within the ladder network to an output node. The Z/2Z ladder network can be implemented within a digital to analog controller (“DAC”), including higher resolution DACs, and high data rate DACs. In higher resolution DACs, and high data rate DACs, the Z/2Z ladder network is coupled through switches to corresponding current sources. The Z/2Z ladder is optionally implemented differentially.
1. An impedance ladder circuit, comprising:
a series connection of n first resistors each having a resistance R, each adjacent pair of the first resistors defining an intermediate node there between, the series of n first resistors defining an output node at a first end and a termination node at a second end;
n second resistors each having a resistance substantially equal to 2R, each second resistor coupled between a respective one of the intermediate nodes and a reference and between the termination node and the reference;
a termination resistor substantially equal to 2R coupled between the termination node and the reference in parallel with one of the second resistors; and
n capacitors, each coupled in parallel with a respective one of the first resistors;
wherein each intermediate node and the termination node has a parasitic capacitance Cp, and wherein each of the n capacitors have a capacitance substantially equal to 2Cp.
2. The circuit according to claim 1 , further comprising n switches, each switch coupled between a respective one of the intermediate nodes and a corresponding current source, and between the termination node and a corresponding current source.
3. The circuit according to claim 2 , wherein the switches are controlled by digital bits.
4. The circuit according to claim 1 , further comprising a load resistance coupled between the output node and the reference.
5. A digital to analog converter, comprising:
a series connection of n first resistors each having a resistance R, each adjacent pair of the first resistors defining an intermediate node there between, the series of n first resistors defining an output node at a first end and a termination node at a second end;
n second resistors each having a resistance substantially equal to 2R, each second resistor coupled between a respective one of the intermediate nodes and a reference, and between the termination node and the reference;
a termination resistor substantially equal to 2R coupled between the termination node and the reference in parallel with one of the second resistors;
n capacitors, each coupled in parallel with a respective one of the first resistors; and
n+1 switches, each coupled between a respective one of the nodes and a respective current source, each said switch controlled by a corresponding digital bit, whereby the termination node switch is controlled by a least significant bit and the output node switch is controlled by a more significant bit;
wherein each intermediate node has an associated capacitance Cp, the termination node has a capacitance substantially equal to 2Cp; and each of the n capacitors have a capacitance substantially equal to 2Cp.
6. The circuit according to claim 5 , wherein the n+1 switches are controlled by digital bits.
7. The circuit according to claim 5 , further comprising:
a load resistance coupled between the output node and the reference; and
one or more additional switches, each coupled between the output node and a respective current source.
8. The circuit according to claim 7 , wherein the additional switches are controlled by a thermometer code generated from most significant bits.
9. An impedance ladder, comprising:
an R/2R ladder network;
capacitors coupled across series resistors within the R/2R ladder network;
wherein the capacitors are sized to substantially match delays from nodes within the R/2R ladder network to an output node;
wherein nodes within the R/2R ladder network include parasitic capacitances, wherein each of the capacitors is substantially equal to twice the parasitic capacitances of a corresponding node.
10. The impedance ladder according to claim 9 , wherein resistors within the R/2R ladder network comprise poly resistors.
11. The impedance ladder according to claim 10 , wherein the capacitors comprise metal finger capacitors.
12. The impedance ladder according to claim 11 , wherein the metal finger capacitors are fabricated on top of the poly resistors.
13. The impedance ladder according to claim 9 , further comprising a second R/2R ladder configured substantially similar to the first R/2R ladder, wherein the first and second R/2R ladders are coupled together by differentially controlled switches.