MOSFET device with localized stressor
MOSFETs having localized stressors are provided. The MOSFET has a stress-inducing layer formed in the source/drain regions, wherein the stress-inducing layer comprises a first semiconductor material and a second semiconductor material. A treatment is performed on the stress-inducing layer such that a reaction is caused with the first semiconductor material and the second semiconductor material is forced lower into the stress-inducing layer. The stress-inducing layer may be either a recessed region or non-recessed region. A first method involves forming a stress-inducing layer, such as SiGe, in the source/drain regions and performing a nitridation or oxidation process. A nitride or oxide film is formed in the top portion of the stress-inducing layer, forcing the Ge lower into the stress-inducing layer. Another method embodiment involves forming a reaction layer over the stress-inducing layer and performing a treatment process to cause the reaction layer to react with the stress-inducing layer.
1 . A semiconductor device comprising:
a gate electrode formed on a substrate; and
source/drain regions formed on either side of the gate electrode;
wherein the source/drain regions comprise a stress-inducing layer comprising a first semiconductor material and a second semiconductor material, concentration of the second semiconductor material being greater at a top surface than at a bottom surface of the stress-inducing layer.
2 . The semiconductor device of claim 1 , wherein the first semiconductor material is silicon and the second semiconductor material is germanium.
3 . The semiconductor device of claim 1 , wherein the concentration of the second semiconductor material is at least 5% greater near the top surface than near the bottom surface of the stress-inducing layer.
4 . The semiconductor device of claim 1 , wherein the top surface of the stress-inducing layer is raised above a surface of the substrate.
5 . The semiconductor device of claim 1 , wherein the stress-inducing layer is from about 10 nm to about 300 nm in thickness.
6 . The semiconductor device of claim 1 , wherein the stress-inducing layer is located in a recess in the substrate.
7 . The semiconductor device of claim 1 , wherein the stress-inducing layer is an elevated stressor such that the stress-inducing layer is formed on a non-recessed portion of the substrate.
8 . The semiconductor device of claim 1 , wherein the stress-inducing layer is positioned from about 0 nm to about 300 nm from the gate electrode.
9 . The semiconductor device of claim 1 , wherein the stress-inducing layer comprises a gradient layer having a varying lattice constant from the top surface to the bottom surface.
10 . The semiconductor device of claim 9 , wherein the gradient layer has a larger lattice constant near the top surface than the bottom surface.
11 . The semiconductor device of claim 9 , wherein a first lattice constant near the top surface is greater than 0.2% of a second lattice constant near the bottom surface of the stress-inducing layer.
12 . A method of forming a semiconductor device, the method comprising:
forming a gate electrode on a substrate;
forming a stress-inducing layer on either side of the gate electrode, the stress-inducing layer comprising a first semiconductor material and a second semiconductor material; and
performing a treatment in an ambient, the treatment causing the first semiconductor material in the stress-inducing layer to react with the ambient creating a depletion layer in a top portion of the stress-inducing layer, the depletion layer being substantially free of the second semiconductor material.
13 . The method of claim 12 , wherein the ambient comprises an oxidation-based gas.
14 . The method of claim 12 , wherein the ambient comprises an oxidation-based gas or a nitridation-based gas.
15 . The method of claim 12 , wherein the performing the treatment is performed at a temperature from about 100° C. to about 1200° C.
16 . The method of claim 12 , wherein the treatment comprises a thermal treatment, a plasma treatment, an ultra-violet treatment, an implant, or a combination thereof.
17 . A method of forming a semiconductor device, the method comprising:
forming a gate electrode on a substrate;
forming a stress-inducing layer on either side of the gate electrode, the stress-inducing layer comprising a first semiconductor material and a second semiconductor material;
forming a reaction layer over the stress-inducing layer; and
performing a treatment, the treatment causing the reaction layer to react with the first semiconductor material in the stress-inducing layer, thereby creating a reacted layer positioned between the reaction layer and the stress-inducing layer, the reacted layer being at least partially composed of material from the stress-inducing layer, the reacted layer being substantially free of the second semiconductor material.
18 . The method of claim 17 , wherein the treatment comprises a thermal anneal, a rapid-thermal anneal, an ultra-violet treatment, or an E-beam curing treatment.
19 . The method of claim 17 , wherein the treatment is performed in an ambient comprising oxygen, nitrogen, or a combination thereof.
20 . The method of claim 17 , wherein the treatment is performed at a temperature from about 100° C. to about 1200° C.