Digital fine delay processing
View Patent ↗Digital fine delay processing provides an accurate and continuous delay for an analog signal generated from source digital data. A digital processor generates processed digital data corresponding to a delayed analog signal having a desired delay relative to the analog signal represented by the source digital data. The processed digital data is directly derived from the source digital data by digital processing, and both digital data are processed by a reference clock, or by the same phase and cycle of the reference clock. The processed digital data is converted into a the delayed analog signal. Modifying coefficients in a convolution function performed by the digital processor changes the desired delay so that the delay is accurately controlled and is continuous. Since the entire process is digital, degradation of the delayed analog signal is minimal.
1. An apparatus for generating a delayed analog signal corresponding to processed digital data that has a user-controlled delay relative to an analog signal corresponding to source digital data, comprising:
a first data generator for generating an n-bit stream of first the source digital data using a first clock;
a clock processor structured to generate a modified clock from the first clock;
a digital convolution processor having a data input for accepting the n-bit stream of the source digital data from the first data generator, having a first clock input for accepting the first clock, having a second clock input for accepting the modified clock, and the digital processor structured to generate, by a convolution function, a second n-bit stream of digital data at a frequency related to a ratio of the first clock and the modified clock; and
a digital-to-analog converter accepting the second n-bit stream of second digital data and structured to generate the delayed analog signal from the second n-bit stream of second digital data that is related to the n-bit stream of first digital data.
2. The apparatus for generating a delayed analog signal corresponding to processed digital data that has a user-controlled delay relative to an analog signal corresponding to source digital data according to claim 1 , in which the modified clock has twice the frequency of the first clock, and in which the second n-bit stream of second digital data is generated at twice the frequency of the n-bit stream first digital data.
3. The apparatus for generating a delayed analog signal corresponding to processed digital data that has a user-controlled delay relative to an analog signal corresponding to source digital data according to claim 2 , wherein the processed digital data has the same cycle and phase as the source digital data.
4. The apparatus for generating a delayed analog signal corresponding to processed digital data that has a user-controlled delay relative to an analog signal corresponding to source digital data according to claim 1 , wherein the digital convolution processor is structured to generate a continuous shift in delay time between the source digital data and the processed digital data using a window function.
5. The apparatus for generating a delayed analog signal corresponding to processed digital data that has a user-controlled delay relative to an analog signal corresponding to source digital data according to claim 4 , wherein the shift in delay time is greater than one clock-cycle resolution.
6. An apparatus for generating a delayed analog signal corresponding to processed digital data that has a user-controlled delay relative to an analog signal corresponding to source digital data, comprising:
a data generator for generating an n-bit stream of the source digital data using a clock signal;
a digital convolution processor having a data input for accepting the n-bit stream of the source digital data from the data generator, having a clock input for accepting the clock signal, and the digital convolution processor structured to generate, by a convolution function, a second n-bit stream of digital data; and
a digital-to-analog converter accepting the second n-bit stream of second digital data and structured to generate the delayed analog signal from the second n-bit stream of second digital data that is related to the n-bit stream of first digital data.
7. An apparatus for generating a delayed analog signal corresponding to processed digital data that has a user-controlled delay relative to an analog signal corresponding to source digital data according to claim 6 , wherein the processed digital data has the same cycle and phase as the source digital data.
8. An apparatus for generating a delayed analog signal corresponding to processed digital data that has a user-controlled delay relative to an analog signal corresponding to source digital data according to claim 6 , wherein the digital convolution processor is structured to generate a continuous shift in delay time between the source digital data and the processed digital data using a window function.
9. The apparatus for generating a delayed analog signal corresponding to processed digital data that has a user-controlled delay relative to an analog signal corresponding to source digital data according to claim 8 , wherein the shift in delay time is greater than one clock-cycle resolution.