High-definition de-interlacing and frame doubling circuit and method
View Patent ↗A combined de-interlacing and frame doubling system ( 114, 114 ′ and 114 ″) advantageously serves to de-interlace successive lines of Present Field Video data at twice the field rate to yield an output bit stream suitable for display on display device that utilizes progressive scanning. The de-interlacing and frame doubling system in accordance with present principles includes a frame memory mechanism ( 116, 116 ′ and 116 ″) for storing at least one frame of interlaced video having a prescribed field rate. At least one de-interlacing circuit ( 1140 1 , 1140′ 1 , 1140 ″) pulls at least two fields of video data from the memory mechanism at a rate of at least twice the field rate for performing a full de-interlacing function in half of a field period to generate the a progressive, frame doubled signal for receipt at the display device.
1. A combined de-interlacing and frame doubling system, comprising:
a unitary frame memory for storing frames of interlaced video data, the frames having a prescribed frame rate;
a unitary circuit for performing both de-interlacing and frame-doubling, said unitary circuit further comprising a de-interlacing mechanism having a pair of de-interlacing circuits that are configured to operate in parallel and each read pixels at the same time from sequential lines of video information stored in the unitary frame memory.
2. The system of claim 1 , wherein said de-interlacing circuits perform the de-interlacing by pulling each of two frames of video data, both from the unitary frame memory, at twice the frame rate and performing a full de-interlacing function at half the frame rate time, thereby effecting two de-interlacing operations, once during each double rate frame, to generate a progressive, frame doubled signal for receipt at a display device.
3. the system of claim 1 , wherein said de-interlacing operations performed in parallel are performed at a conventional clock speed.
4. A method for de-interlacing interlaced video, comprising the steps of:
reading from a unitary memory each of two frames of video information at a rate of twice a normal frame rate;
performing, at a unitary combined de-interlacing and frame doubling circuit, two de-interlacing operations in parallel with each other and at the same time, each de-interlacing operation being performed on a successive pair of video lines separate from the other de-interlacing operation.
5. The method according to claim 4 , wherein said two de-interlacing operations are performed at a conventional clock speed.
6. The method according to claim 5 further comprising the step of writing updated information after each of the two interlacing operations into a memory associated with that operation for access during the other of the de-interlacing operations.