CMOS active pixel sensor with improved dark current and sensitivity
View Patent ↗An active pixel sensor which provides reduced dark current, improved sensitivity, and improved modulation transfer function. An N well, surrounded by a P well is formed in a P type epitaxial substrate. A P + region is formed extending from within the P well into the substrate leaving a gap between the P + region and the N well. A gate dielectric is formed covering at least the gap, part of the P + region, and part of the N well. A gate electrode is formed on the gate dielectric over the gap, part of the P + region, and part of the N well. The gate electrode is biased so that the region of the substrate under the gate electrode is accumulated with holes and the region of the N well under the gate electrode is depleted of electrons. This will reduce the dark current and improve the sensitivity of the active pixel sensor. In a second embodiment the P type epitaxial substrate is replaced by an N type epitaxial substrate, the N well is replaced by a P well, N + regions are replaced by P + regions, and P + regions are replaced by N + regions. In this second embodiment the gate electrode is biased so that the region of the substrate under the gate electrode is depleted of electrons and the region of the P well under the gate electrode is accumulated with holes.
1. An active pixel sensor, comprising:
a substrate formed of P type epitaxial silicon;
an N well formed in said substrate wherein said N well is formed of N type silicon;
a P well formed in said substrate wherein said P well has an inner periphery and an outer periphery, surrounds said N well, and is formed of P type silicon;
an N + region formed in said N well, wherein the entire said N + region is within said N well and does not extend beyond said N well;
a P + region formed in part of said P well and part of said substrate wherein said P + region extends from within said P well into said substrate toward said N well, thereby leaving a gap between said P + region and said N well;
a layer of gate dielectric formed over said gap, said N well, said N + region, and at least part of said P + region; and
a gate electrode formed on said layer of gate dielectric over said gap, at least part of said N well, and at least part of said P + region.
2. The active pixel sensor of claim 1 wherein said gate dielectric is formed over all of said P + region.
3. The active pixel sensor of claim 1 wherein said gate dielectric is silicon dioxide.
4. The active pixel sensor of claim 1 wherein said gate electrode is formed of polysilicon.
5. The active pixel sensor of claim 1 further comprising a shallow trench isolation region in said P well.
6. The active pixel sensor of claim 1 further comprising an opaque shield over said active pixel sensor except for said P + region, said gap, said N region, and said N + region.
7. The active pixel sensor of claim 6 wherein said opaque shield is a metal shield.
8. The active pixel sensor of claim 1 wherein said gate electrode is held at the lowest potential of the active pixel sensor.
9. The active pixel sensor of claim 1 wherein electrical contact to said N well is made through said N + region.
10. An active pixel sensor, comprising:
a substrate formed of N type epitaxial silicon;
a P well formed in said substrate wherein said P well is formed of P type silicon;
an N well formed in said substrate wherein said N well has an inner periphery and an outer periphery, surrounds said P well, and is formed of N type silicon;
a P + region formed in said P well, wherein the entire said P + region is within said P well and does not extend beyond said P well;
an N + region formed in part of said N well and part of said substrate wherein said N + region extends from within said N well into said substrate toward said P well, thereby leaving a gap between said N + region and said P well;
a layer of gate dielectric formed over said gap, said P well, said P + region, and at least part of said N + region; and
a gate electrode formed on said layer of gate dielectric over said gap, at least part of said P well, and at least part of said N + region.
11. The active pixel sensor of claim 10 wherein said gate dielectric is formed over all of said N + region.
12. The active pixel sensor of claim 10 wherein said gate dielectric is silicon dioxide.
13. The active pixel sensor of claim 10 wherein said gate electrode is formed of polysilicon.
14. The active pixel sensor of claim 10 further comprising a shallow trench isolation region in said N well.
15. The active pixel sensor of claim 10 further comprising an opaque shield over said active pixel sensor except for said N + region, said gap, said P region, and said P + region.
16. The active pixel sensor of claim 15 wherein said opaque shield is a metal shield.
17. The active pixel sensor of claim 10 wherein said gate electrode is held at the highest potential of the active pixel sensor.
18. The active pixel sensor of claim 10 wherein electrical contact to said P well is made through said P + region.