Intelligent memory array switching logic
Techniques and circuitry that support switching operations required to exchange data between memory arrays and external data pads are provided. In a write path, such switching operations may include latching in and assembling a number of bits sequentially received over a single data pad, reordering those bits based on a type of access mode (e.g., interleaved or sequential), and performing scrambling operations based on chip organization (e.g., ×4, ×8, or ×16) a bank location being accessed. Similar operations may be performed (in reverse order) in a read path, to assemble data to be read out of a device.
1 . A memory device capable of sequentially transferring a plurality of data bits via a plurality of data pads in a single cycle of an external clock signal, comprising:
one or more memory arrays;
a plurality of data pads; and
array switching logic driven by a core clock signal having a frequency one half or less than that of the external clock signal and configured to scramble a plurality of data bits sequentially received via the data pads prior to writing the bits of data to the memory arrays and to scramble a plurality of data bits read from the memory arrays prior to sequentially outputting the bits of data via the data pads.
2 . The memory device of claim 1 , wherein the scrambling performed by the array switching logic is dependent, at least in part, on a physical location of targeted memory cells.
3 . The memory device of claim 2 , wherein the scrambling performed by the array switching logic is dependent, at least in part, on a physical location of targeted memory cells relative to a twist region.
4 . The memory device of claim 1 , wherein the scrambling performed by the array switching logic is dependent, at least in part, on a bit-width organization of the memory device.
5 . A pipelined data path for transferring data between one or more memory arrays and a plurality of data pads, comprising:
pad logic configured to, receive, on each of a plurality of data pads, N-bits of data sequentially at a data frequency and output the N-bits of data in the ordered received in parallel to the reordering logic on the first set of data lines;
reordering logic configured to reorder bits of data received in parallel on a first set of data lines and present the reordered bits on a second set of data lines; and
array switching logic driven at a core frequency configured to scramble bits of data received from reordering logic on the second set of data lines onto a third set of data lines to be written to the memory arrays, wherein the data frequency is at least twice the core frequency.
6 . The data path of claim 5 , wherein the scrambling performed by the array switching logic is dependent, at least in part, on a physical location of targeted memory cells.
7 . The data path of claim 5 , wherein the scrambling performed by the array switching logic is dependent, at least in part, on a bit-width organization of the memory device.
8 . The data path of claim 5 , wherein the second set of data lines is oriented substantially perpendicular to the third set of data lines.
9 . The data path of claim 5 , wherein the array switching logic comprises an array of substantially identical switch matrix structures.
10 . The data path of claim 9 , wherein each switch matrix structure comprises a plurality of switches to selectively couple 1 to N of the second set of data lines to 1 to N of the third set of data lines.
11 . A memory device capable of sequentially transferring a plurality of data bits via a plurality of data pads in a single cycle of an external clock signal, comprising:
one or more memory arrays;
a plurality of data pads;
pad logic configured to, receive, on each of a plurality of data pads, N-bits of data sequentially at a data frequency and output the N-bits of data in the order received in parallel on a first set of data lines;
reordering logic configured to reorder bits of data received in parallel on the first set of data lines and present the reordered bits on a second set of data lines; and
array switching logic driven by a core clock signal having a frequency one half or less than that of the external clock signal and configured to scramble a plurality of data bits sequentially received via the data pads prior to writing the bits of data to the memory arrays and to scramble a plurality of data bits read from the memory arrays prior to sequentially outputting the bits of data via the data pads.
12 . The memory device of claim 11 , wherein the reordering logic is also driven by the core clock signal.
13 . The memory device of claim 11 , wherein the scrambling performed by the array switching logic is dependent on a bit-width organization of the memory device and a physical location of targeted memory cells.
14 . The memory device of claim 13 , wherein:
the array switching logic comprises a plurality of substantially identical switch matrices; and
each switch matrix comprises an arrangement of switches arranged to selectively couple one or more of the second set of data lines to one or more of the third set of data lines.
15 . The memory device of claim 14 , wherein:
if a first bit-width organization is selected, a limited number of the second set of data lines are selectively coupled to the third set of data lines; and
if a second bit-width organization is selected, all of the second set of data lines are coupled to the third set of data lines.
16 . The memory device of claim 13 , wherein the memory arrays are separated by a twist region and, the scrambling performed by the array switching logic is dependent, at least in part, on a location of a memory array being accessed relative to the twist region.
17 . The memory device of claim 13 , wherein the arrangement of switches is configured such that:
when a particular memory organization is selected, no two adjacent switches in a single matrix are closed simultaneously.
18 . A method of exchanging data with a memory device, comprising:
receiving N bits of data sequentially on each of a plurality of data pads within a single cycle of an external clock signal;
presenting the N bits of data in parallel on a first set of data lines;
reordering the N bits of data onto a second set of data lines; and
scrambling the reordered bits of data onto a third set of data lines in conjunction with an internal core clock signal having a frequency one half or less than that of the external clock signal.
19 . The method of claim 18 , wherein the scrambling comprises selectively coupling one or more of the second set of data lines with one or more of the third set of data lines based, at least in part, on a bit-width organization of the memory device.
20 . The method of claim 18 , wherein the scrambling comprises selectively coupling one or more of the second set of data lines with one or more of the third set of data lines based, at least in part, on a physical location of targeted memory cells.
21 . The method of claim 18 , wherein reordering the N bits of data onto a second set of data lines is performed in conjunction with the core clock signal.