Transimpedance amplifier

1. A transimpedance amplifier (TIA) circuit, comprising:

an input;

an amplifying stage that includes N amplifiers, that generates a first signal and that is AC coupled to said input, where N is an integer greater than zero;

a bias stage that generates and outputs a second signal and that is DC coupled to said input; and

an output stage driven by said first signal, which is combined with and biased by said second signal.

2. A transimpedance amplifier (TIA) circuit, comprising:

an input;

an amplifying stage that includes N amplifiers, that generates a first signal and that is AC coupled to said input, where N is an integer greater than zero;

a bias stage that generates a second signal and that is DC coupled to said input; and

an output stage driven by said first signal and said second signal;

wherein said N amplifiers are connected in series and each includes an input, an output, and a feedback resistance.

3. A transimpedance amplifier (TIA) circuit, comprising:

an input;

an amplifying stage that includes N amplifiers, that generates a first signal and that is AC coupled to said input, where N is an integer greater than zero;

a bias stage that generates a second signal and that is DC coupled to said input; and

an output stage driven by said first signal and said second signal;

wherein said bias stage comprises an op-amp having a non-inverting input that communicates with said input.

4. The TIA of claim 3 wherein said bias stage further comprises:

a first current source; and

a first transistor having first and second terminals and a control terminal,

wherein said first current source communicates with said second terminal of said first transistor and an inverting input of said op-amp.

5. A transimpedance amplifier (TIA) circuit, comprising:

an input;

an amplifying stage that includes N amplifiers, that generates a first signal and that is AC coupled to said input, where N is an integer greater than zero;

a bias stage that generates a second signal and that is DC coupled to said input;

an output stage driven by said first signal and said second signal; and

a low pass filter that communicates with said bias stage.

6. A transimpedance amplifier (TIA) circuit, comprising:

an input;

an amplifying stage that includes N amplifiers, that generates a first signal and that is AC coupled to said input, where N is an integer greater than zero;

a bias stage that generates a second signal and that is DC coupled to said input;

an output stage driven by said first signal and said second signal; and

a current limiting device that communicates with said bias stage and said output stage.

7. A transimpedance amplifier (TIA) circuit, comprising:

an input;

an amplifying stage that includes N amplifiers, that generates a first signal and that is AC coupled to said input, where N is an integer greater than zero;

a bias stage that generates a second signal and that is DC coupled to said input; and

an output stage driven by said first signal and said second signal;

wherein said output stage comprises:

a first current source; and

a first transistor having first and second terminals and a control terminal,

wherein said first current source communicates with said second terminal of said first transistor.

8. A transimpedance amplifier (TIA) circuit, comprising:

an input;

an amplifying stage that includes N amplifiers, that generates a first signal and that is AC coupled to said input, where N is an integer greater than zero;

a bias stage that generates a second signal and that is DC coupled to said input and that comprises:

a first current source; and

a first transistor having first and second terminals and a control terminal, wherein said first current source communicates with said second terminal of said first transistor and an inverting input of said op-amp; and

an output stage driven by said first signal and said second signal and wherein said output stage comprises:

a second current cource; and

a second transistor having second and second terminals and a control terminal,

wherein said second current source communicates with said second terminal of said second transistor,

wherein said first current source provides a magnitude of current flow that is a fraction of the magnitude of current flowing through said second current source.

9. A transimpedance amplifier (TIA) circuit, comprising:

an input;

an amplifying stage that includes N amplifiers, that generates a first signal and that is AC coupled to said input, where N is an integer greater than zero;

a bias stage that generates a second signal and that is DC coupled to said input; and

an output stage driven by said first signal and said second signal;

wherein said output stage is DC-coupled to said input via a feedback circuit.

10. A transimpedance amplifier (TIA) circuit for amplifying an input signal, comprising:

an amplifying stage that amplifies signals in a first frequency range and that has an input and an output;

a bias stage that has an input and an output and that generates a bias signal;

a signal input node that communicates said input of said amplifying stage and said input of said bias stage;

an output stage that communicates with outputs of said amplifying and bias stages, wherein said output stage includes a signal output node; and

a feedback path DC that communicates with said signal output node and said signal input node.

11. The TIA of claim 10 wherein said amplifying stage comprises N amplifiers connected in series with a capacitor, each of said N amplifiers including an input, an output, and a feedback resistance.

12. The TIA of claim 10 wherein said bias stage comprises an op-amp having a non-inverted input that communicates with said input.

13. The TIA of claim 12 wherein said bias stage further comprises a current source connected to said op-amp.

14. The TIA of claim 10 further comprising a capacitor having one end that communicates with said bias stage and an opposite end that communicates with a reference node.

15. The TIA of claim 10 further comprising a current limiting device that communicates with said bias stage and said output stage.

16. The TIA of claim 10 wherein said output stage has a first output device, and said bias stage has a second output device, wherein said first and second output devices are performance matched.

17. The TIA of claim 13 wherein said current source provides a fraction of the current flowing through a bias source of said output stage.

18. A transimpedance amplifier (TIA) circuit, comprising:

input means for receiving an input;

amplifying stage means for amplifying that includes N amplifying means for amplifying, that generates a first signal and that is AC coupled to said input means, where N is an integer greater than zero;

bias means comprising at least one transistor means for generating a second signal, wherein said bias means is DC coupled to said input means; and

output means for generating an output and that is driven by said first signal means and said second signal.

19. A transimpedance amplifier (TIA) circuit, comprising:

input means for receiving an input;

amplifying stage means for amplifying that includes N amplifying means for amplifying, that generates a first signal and that is AC coupled to said input means, where N is an integer greater than zero;

bias means comprising at least one for generating a second signal and that is DC coupled to said input means; and

output means for generating an output and that is driven by said first signal means and said second signal;

wherein said N amplifying means each include an input, an output, and a feedback means for providing resistance.

20. A transimpedance amplifier (TIA) circuit, comprising:

input means for receiving an input;

amplifying stage means for amplifying that includes N amplifying means for amplifying, that generates a first signal and that is AC coupled to said input means, where N is an integer greater than zero;

bias means comprising at least one for generating a second signal and that is DC coupled to said input means; and

output means for generating an output and that is driven by said first signal means and said second signal;

wherein said bias means comprises operational amplifying means for amplifying and having a non-inverting input that communicates with said input means.

21. The TIA of claim 20 wherein said bias means further comprises:

first current means for providing current; and

a first transistor having first and second terminals and a control terminal,

wherein said first current means communicates with said second terminal of said first transistor and an inverting input of said operational amplifying means.

22. A transimpedance amplifier (TIA) circuit, comprising:

input means for receiving an input;

amplifying stage means for amplifying that includes N amplifying means for amplifying, that generates a first signal and that is AC coupled to said input means, where N is an integer greater than zero;

bias means comprising at least one for generating a second signal and that is DC coupled to said input means;

output means for generating an output and that is driven by said first signal means and said second signal; and

filter means for filtering and that communicates with said bias means.

23. A transimpedance amplifier (TIA) circuit, comprising:

input means for receiving an input;

amplifying stage means for amplifying that includes N amplifying means for amplifying, that generates a first signal and that is AC coupled to said input means, where N is an integer greater than zero;

bias means comprising at least one for generating a second signal and that is DC coupled to said input means;

output means for generating an output and that is driven by said first signal means and said second signal; and

current limiting means for limiting current and that communicates with said bias means and said output means.

24. The TIA of claim 21 wherein said output means further comprises:

second current means for providing current; and

a second transistor having first and second terminals and a control terminal,

wherein said second current means communicates with said second terminal of said second transistor.

25. The TIA of claim 24 wherein said first current means provides a magnitude of current flow that is a fraction of the magnitude of current flowing through said second current means.

26. A transimpedance amplifier (TIA) circuit, comprising:

input means for receiving an input;

amplifying stage means for amplifying that includes N amplifying means for amplifying, that generates a first signal and that is AC coupled to said input means, where N is an integer greater than zero;

bias means comprising at least one for generating a second signal and that is DC coupled to said input means; and

output means for generating an output and that is driven by said first signal means and said second signal;

wherein said output means is DC-coupled to said input means via a feedback means.

27. A transimpedance amplifier (TIA) circuit for amplifying an input signal, comprising:

amplifying stage means for amplifying signals in a first frequency range and having an input and an output;

bias means for generating a bias signal and having an input and an output;

input means for receiving input signals and that communicates with said input of said amplifying stage means and said input of said bias means;

output means for generating an output and that communicates with outputs of said amplifying stage means and said bias means; and

feedback means for providing feedback and that is DC coupled between said output means and said input means.

28. The TIA of claim 27 wherein said amplifying stage means comprises N amplifying means for amplifying connected in series with capacitance means for providing capacitance, each of said N amplifying means including an input, an output, and resistance means for providing resistance.

29. The TIA of claim 27 wherein said bias means comprises operational amplifying means for amplifying and having a non-inverted input that communicates with said input means.

30. The TIA of claim 29 wherein said bias means further comprises current means for providing current and that communicates with said operational amplifying means.

31. The TIA of claim 27 further comprising capacitance means for providing a capacitance and having one end that communicates with an output of said bias means and an opposite end that communicates with a reference node.

32. The TIA of claim 27 further comprising current limiting means for limiting current and that communicates with said bias means and said output means.

33. The TIA of claim 27 wherein said output means includes first output means for generating an output, and said bias means includes second output means for generating an output, wherein said first and second output means are performance matched.

34. The TIA of claim 30 wherein said current means provides a fraction of the current flowing through a bias source of said output means.

35. A method for providing a transimpedance amplifier (TIA) circuit, comprising:

providing input signals to an input;

providing an amplifying stage including N amplifiers;

AC coupling said amplifying stage to said input;

generating a first signal using said amplifying stage;

generating and outputing a second signal using a bias stage that is DC coupled to said input; and

generating an output based on said first signal biased by said second signal.

36. A method for providing a transimpedance amplifier (TIA) circuit, comprising:

providing input signals to an input;

providing an amplifying stage including N amplifiers, where N is an integer greater than zero;

AC coupling said amplifying stage to said input;

generating a first signal using said amplifying stage;

generating a second signal using a bias stage that is DC coupled to said input;

generating an output based on said first signal and said second signal; and

connecting said N amplifiers in series, wherein each of said N amplifiers include an input, an output, and a feedback resistance.

37. A method for providing a transimpedance amplifier (TIA) circuit, comprising:

providing input signals to an input;

providing an amplifying stage including N amplifiers, where N is an integer greater than zero;

AC coupling said amplifying stage to said input;

generating a first signal using said amplifying stage;

generating a second signal using a bias stage that is DC coupled to said input;

generating an output based on said first signal and said second signal; and

wherein said bias stage comprises an op-amp having a non-inverting input that communicates with said input.

38. A method for providing a transimpedance amplifier (TIA) circuit, comprising:

providing input signals to an input;

providing an amplifying stage including N amplifiers, where N is an integer greater than zero;

AC coupling said amplifying stage to said input;

generating a first signal using said amplifying stage;

generating a second signal using a bias stage that is DC coupled to said input;

generating an output based on said first signal and said second signal; and

filtering an output of said bias stage.

39. A method for providing a transimpedance amplifier (TIA) circuit, comprising:

providing input signals to an input;

providing an amplifying stage including N amplifiers, where N is an integer greater than zero;

AC coupling said amplifying stage to said input;

generating a first signal using said amplifying stage;

generating a second signal using a bias stage that is DC coupled to said input;

generating an output based on said first signal and said second signal; and

limiting current flowing between said bias stage and said output.

40. A method for providing a transimpedance amplifier (TIA) circuit, comprising:

providing input signals to an input;

providing an amplifying stage including N amplifiers, where N is an integer greater than zero;

AC coupling said amplifying stage to said input;

generating a first signal using said amplifying stage;

generating a second signal using a bias stage that is DC coupled to said input;

generating an output based on said first signal and said second signal using an output stage; and

DC-coupling said output to said input.