Smart start-up circuit for switching regulators
View Patent ↗The smart start-up circuits basically include a sensor, two stacked PMOS transistors, two stacked NMOS transistors, and a feedback line. If the sensing voltage does not reach the expected voltage compared to the midpoint voltage of the sensor, the output voltage of the sensor turns on the corresponding transistor, which provides a current to its output until the voltage at feedback reaches the midpoint voltage. The time to reach the midpoint voltage at a load is simply equal to the charge stored at the load divided by the current, which can be scaled by a device aspect ratio of the transistor. Consequently, all smart start-up circuits provide an initial output voltage level closer to the output voltage level that reaches the equilibrium according to schedule.
1. A smart start-up circuit for providing an initial output voltage level closer to an output voltage level of a switching regulator that reaches an equilibrium according to schedule, comprising:
a feedback line connected with an output and an input of the smart start-up circuit, which become a single node coupled to a load, wherein the single node of the smart start-up circuit is connected to an output terminal of the switching regulator;
a sensor for sensing a voltage at the output, comparing with the midpoint voltage of the sensor, and providing its output;
two stacked PMOS transistors connected between a power supply and the output; and
two stacked NMOS transistors connected between the output and ground.
2. The circuit as recited in claim 1 wherein the sensor is a low-voltage sensor which has an input and an output.
3. The circuit as recited in claim 2 wherein the low-voltage sensor's output is coupled to a gate terminal of an upper PMOS transistor of the two stacked PMOS transistors.
4. The circuit as recited in claim 1 wherein the sensor is a high-voltage sensor which has an input and an output.
5. The circuit as recited in claim 4 wherein the high-voltage sensor's output is coupled to a gate terminal of a lower NMOS transistor of the two stacked NMOS transistors.
6. The circuit as recited in claim 1 wherein the sensor is both a low-voltage sensor and a high-voltage sensor.
7. The circuit as recited in claim 6 wherein the low-voltage sensor's output is coupled to the gate terminal of the upper PMOS transistor and the high-voltage sensor's output is coupled to the gate terminal of the lower NMOS transistor.
8. The circuit as recited in claim 1 wherein the sensor is an even number of inverters.
9. The circuit as recited in claim 1 wherein the sensor is a comparator which has an input and an output.
10. The circuit as recited in claim 1 further comprising a power-down NMOS transistor so that the power-down NMOS transistor provides an output pull-down path to ground when a power-down input voltage is high during power-down mode.
11. The circuit as recited in claim 10 wherein the output of the smart start-up circuit is coupled to a load connected between the output and ground and also coupled to the output terminal of the switching regulator.
12. The circuit as recited in claim 10 wherein the output of the smart start-up circuit is at ground when the power-down NMOS transistor has a gate terminal which is connected to the power-down input.
13. The circuit as recited in claim 1 further comprising a power-down PMOS transistor and a power-down inverter so that the power-down PMOS transistor provides an output pull-up path to the power supply when a power-down input voltage is high during power-down mode.
14. The circuit as recited in claim 13 wherein the output of the smart start-up circuit is coupled to a load connected between the output and the power supply and also coupled to the output terminal of the switching regulator.
15. The circuit as recited in claim 13 wherein the output of the smart start-up circuit is at the power supply when the power-down PMOS transistor has a gate terminal which is inverted from the power-down input through the power-down inverter.
16. The circuit as recited in claim 13 wherein the power-down inverter used in the smart start-up circuit is an odd number of inverters.
17. The circuit as recited in claim 1 wherein the smart start-up circuit is developed for use in all switching regulators without regard to architectures, topologies, and schematics.