Gate electrode for FinFET device
View Patent ↗In a method of forming a semiconductor device, a self-planarizing conductive layer is formed over a substrate that includes a topography having sharp drop-offs. The self-planarizing conductive layer is characterized by a substantially flatter surface than the underlying topography. As a result of the self-planarizing layer, a masking layer having a more uniform thickness may be formed over the conductive layer. Because the masking layer has a more uniform thickness, the masking layer may easily be patterned without causing damage to the underlying materials. These techniques may be used to fabricate, among other things, a FinFET without parasitic spacers formed around the fins and the source/drain regions.
1. A method of forming a FinFET, the method comprising:
forming a source region on a substrate;
forming a drain region on the substrate;
forming one or more fins interconnecting the source region and the drain region;
forming a self-planarizing conductive layer by spin-coating a layer of polymer based material over the substrate and the one or more fins, the self-planarizing conductive layer having a substantially flatter topography than an underlying topography;
forming a mask layer over the self-planarizing conductive layer;
patterning the mask layer to define a gate electrode; and
removing excess portions of the self-planarizing conductive layer such that remaining portions of the self-planarizing conductive layer form the gate electrode.
2. The method of claim 1 , wherein the polymer-based material comprises a polymer with metallic particles.
3. The method of claim 2 , wherein the metallic particles comprise particles of a refractory metal, a noble metal, or a combination thereof.
4. A method of forming a FinFET, the method comprising:
forming a source region on a substrate;
forming a drain region on the substrate;
forming one or more fins interconnecting the source region and the drain region;
forming a self-planarizing conductive layer over the substrate and the one or more fins, the self-planarizing conductive layer having a substantially flatter topography than an underlying topography, wherein the forming the self-plan conductive layer is performed by depositing a metal organic film and heating the metal organic film, thereby evaporating organic materials of the metal organic film and forming a conductive layer;
forming a mask layer over the self-planarizing conductive layer;
patterning the mask layer to define a gate electrode; and
removing excess portions of the self-planarizing conductive layer such that remaining portions of the self-planarizing conductive layer form the gate electrode.
5. A method of forming a FinFET, the method comprising:
forming a source region on a substrate;
forming a drain region on the substrate;
forming one or more fins interconnecting the source region and the drain region;
forming self-planarizing conductive layer over the substrate and the one or more fins, the self-planarizing conductive layer having a substantially flatter topography than an underling topography, wherein the forming the self-planarizing conductive layer is performed by depositing a conductive layer over the substrate and subjecting the conductive material to pressure sufficient to substantially planarize the conductive layer;
forming a mask layer over the self-planarizing conductive layer;
patterning the mask layer to define a gate electrode; and
removing excess portions of the self-planarizing conductive layer such that remaining portions of the self-planarizing conductive layer form the gate electrode.
6. The method of claim 1 , wherein the self-planarizing conductive layer comprises a metal-filled polymer.
7. The method of claim 5 , wherein the self-planarizing conductive layer includes a metal-alloy, a metal-oxide, or a combination thereof.
8. A transistor formed on a substrate, the transistor comprising:
a source region formed on the substrate;
a drain region formed on the substrate;
one or more fins interconnecting the source region and the drain region; and
a gate electrode overlying the fins, a surface of the gate electrode having a substantially planar surface, wherein the gate electrode comprises a polymer with metallic particles.
9. The transistor of claim 8 , wherein the metallic particles comprise particles of a refractory metal, a noble metal, or a combination thereof.
10. The transistor of claim 8 , wherein the gate electrode comprises a metallic film.
11. The transistor of claim 8 , wherein the gate electrode has a thickness about 100 Å to about 1000 Å above the fins.
12. The transistor of claim 8 , wherein the gate electrode comprises a dual-gate electrode.
13. The transistor of claim 8 , wherein the gate electrode comprises a triple-gate electrode.
14. The transistor of claim 8 , wherein the gate electrode is formed from a material comprising a metal-filled polymer, an organic polymer, or a combination thereof.
15. The transistor of claim 8 , wherein the gate electrode is formed from a metal-alloy, a metal-oxide, or a combination thereof.
16. The method of claim 1 , wherein the self-planarizing conductive layer comprises an organic polymer.
17. A transistor formed on a substrate, the transistor comprising:
a source region formed on the substrate;
a drain region formed on the substrate;
one or more fins interconnecting the source region and the drain region; and
a gate electrode overlying the fins, a surface of the gate electrode having a substantially planar surface, wherein the gate electrode is formed from a liquid metal.
18. The transistor of claim 17 , wherein the gate electrode has a thickness about 100 Å to about 1000 Å above the fins.
19. The transistor of claim 17 , wherein the gate electrode comprises a dual-gate electrode.
20. The transistor of claim 17 , wherein the gate electrode comprises a triple-gate electrode.