Non-volatile memory resistor cell with nanotip electrode

1. A method for fabricating a nanotip electrode non-volatile memory resistor cell, the method comprising:

forming a first electrode with nanotips;

forming a memory resistor material adjacent the nanotips;

forming a second electrode adjacent the memory resistor material, where the memory resistor material is interposed between the first and second electrodes;

wherein forming the first electrode with nanotips includes forming a bottom electrode with nanotips having nanotip ends; and,

wherein forming the memory resistor material adjacent the nanotips includes:

conformally deposting the memory resistor material overlying the bottom electrode with nanotips; and

planarizing the memory resistor material; and

wherein forming the second electrode includes forming a top electrode overlying the memory resistor material.

2. The method of claim 1 wherein forming the first electrode with nanotips includes forming nanotips having a tip base size of about 50 nanometers, or less.

3. The method of claim 1 wherein forming the first electrode with nanotips includes forming nanotips having a tip height in the range of 5 to 50 nm.

4. The method of claim 1 wherein forming the first electrode with nanotips includes forming nanotips having a nanotip density of greater than 100 nanotips per square micrometer.

5. The method of claim 1 wherein forming the first electrode with nanotips includes forming iridium oxide (IrOx) nanotips.

6. The method of claim 5 further comprising:

providing a substrate, made from a material selected from the group including silicon, silicon oxide, silicon nitride, and noble metals;

wherein forming IrOx nanotips includes:

supplying a (Methylcyclopendieyl)(1,5-cycleectahiene) precursor;

depositing Ir using a metalorganic chemical vapor deposition (MOCVD) process; and

growing IrOx nanotips from the deposited Ir.

7. The method of claim 6 wherein forming IrOx nanotips further includes:

depositing the Ir at a temperature of about 350° C.; and

depositing the Ir at an oxygen partial pressure in the range of 10 to 50 torr.

8. The method of claim 6 further comprising:

forming a refractory metal film overlying the substrate; and

wherein depositing Ir using an MOCVD process includes depositing Ir overlying the refractor metal film.

9. The method of claim 1 wherein forming the memory resistor material adjacent the nanotips includes forming a memory resistor material selected from the group including Pr 0.3 Ca 0.7 MnO 3 (PCMO), colossal magnetoresistive (CMR) film, transition metal oxides, Mott insulators, and high-temperature super conductor (HTSC) material.

10. The method of claim 1 wherein conformally depositing the memory resistor material includes conformally depositing memory resistor material, having a thickness in the range of 50 to 200 nm, overlying the nanotips; and

wherein planarizing the memory resistor material includes leaving a thickness of memory resistor material, in the range of 30 to 200 nm, interposed between the nanotip ends and the top electrode.

11. The method of claim 1 wherein forming the top electrode includes:

conformally depositing top electrode material;

selectively etching the top electrode material, memory resistor material, and the bottom electrode; and

the method further comprising:

forming a passivation layer adjacent the memory cell.

12. The method of claim 1 wherein forming the second electrode includes forming a second electrode from a material selected from the group including Pt, refractory metals, refractory metal oxides, refractory metal nitrides, and Al.

13. The method of claim 1 wherein forming the memory resistor material adjacent the nanotips includes forming the memory resistor material adjacent the nanotips in a relationship selected from the group of surrounding the nanotips, on the nanotips, and between the nanotips.