Level conversion circuit and semiconductor integrated circuit device employing the level conversion circuit
View Patent ↗In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.
1. A semiconductor integrated circuit device comprising:
a first area including a first circuit supplied with a first supply voltage;
a second area including a second circuit supplied with a second supply voltage;
wherein the first circuit includes a level conversion circuit, a pre-buffer coupled to the level conversion circuit, and an NMOS output buffer and a PMOS output buffer coupled to a I/O pad and driven by the pre-buffer,
wherein the second circuit includes a logic circuit to output a signal to the level conversion circuit, and
wherein the signal is transmitted to the first circuit via a first electrostatic breakdown protective circuit and the first electrostatic breakdown protective circuit is provided in the first area.
2. The semiconductor integrated circuit device according to claim 1 ,
wherein the pre-buffer, PMOS output buffer and NMOS output buffer are arranged serially.
3. The semiconductor integrated circuit device according to claim 2 ,
wherein the pre-buffer and the NMOS output buffer are coupled via a second electrostatic breakdown protective circuit, and
wherein the prebuffer and the PMOS output buffer are coupled via a third electrostatic breakdown protective circuit.
4. The semiconductor integrated circuit device according to claim 1 ,
wherein a first reference potential of the first supply voltage and a second reference potential of the second supply voltage are connected electrically outside of the semiconductor integrated circuit device.
5. The semiconductor integrated circuit device according to claim 4 ,
wherein the first reference potential and the second reference potential are connected electrically on a board on which the semiconductor integrated circuit device is mounted.
6. The semiconductor integrated circuit device according to claim 1 ,
wherein the first circuit includes a first MOS transistor and the second circuit includes a second MOS transistor, and
wherein a gate insulated film of the first MOS transistor is thicker than a gate insulated film of the second MOS transistor.