Non-linear compensation of timing jitter
View Patent ↗Systems and methods for compensating transitions in a data stream to account for jitter including laser jitter. Transitions in the data stream are delayed or advanced depending on the laser jitter and/or whether the previous transition is a rising or falling transition. The compensation of transitions is non-linear such that compensation applied to a rising transition is not necessarily the same as compensation applied to a falling transition. A history of more than one or more bits or transitions of the data stream can be used to further adjust the compensation of transitions in the data stream. When a transition is detected, the bit following the detected transition is peaked either positively or negatively such that the following transition is accordingly delayed or advanced.
1. A circuit for compensating for laser jitter in a data stream that is transmitted by a laser included in an optical transmitter, the circuit comprising:
a transition detector that detects transitions in a data stream;
a gain circuit that provides gain to the data stream when transitions are detected by the transition detector;
a pulse shaper that delays the data stream while the transition detector detects transitions; and
a summer that sums the gain from the gain circuit with the data stream that is delayed by the pulse shaper such that the transitions in the data stream are compensated for at least laser jitter of the laser.
2. A circuit as defined in claim 1 , wherein the transition detector further comprises a first delay element and a second delay element in series.
3. A circuit as defined in claim 2 , wherein the first delay element Delays the data stream for half a period and the second delay element delays the data stream for a full period.
4. A circuit as defined in claim 2 , wherein the transition detector further comprises:
a first logic gate connected to the first delay element and the second delay element; and
a second logic gate connected to the first delay element and the second delay element.
5. A circuit as defined in claim 4 , wherein the first logic gate detects a falling transition and the second logic gate detects a rising transition.
6. A circuit as defined in claim 5 , wherein the gain circuit receives outputs of the first logic gate and the second logic gate and provides the gain associated with the transitions in the data stream based in part on the outputs of the first logic gate and the second logic gate.
7. A circuit as defined in claim 1 , wherein the pulse shaper shapes the transitions in the data stream.
8. A circuit as defined in claim 1 , wherein rising transitions are compensated by a first gain and falling transitions are compensated by a second gain.
9. A method for compensating transitions of a data stream for laser jitter, the method comprising:
storing a history of at least one bit of the data stream, wherein the history includes a current bit, wherein storing a history of at least one bit further comprises delaying the data stream with a first delay element and a second delay element;
detecting at least one transition in the data stream based on the history of at least one bit, the at least one transition including a transition occurring after the current bit, wherein detecting at least one transition in the data stream further comprises:
detecting a falling transition with a first AND gate having as inputs an inverted output of the first delay element and an output of the second delay element; and
detecting a rising transition with a second AND gate having as inputs the output of the first delay element and an inverted output of the second delay element;
compensating the current bit either positively or negatively such that the transition occurring after the current bit is compensated in the data stream, wherein compensating the current bit such that the transition is compensated in the data stream further comprises weighting an output of the first AND gate and of the second AND gate; and
summing the weighted output of the first AND gate and the second AND gate with an output of the pulse shaper such that the current bit in the data stream is peaked before the current transition, thereby compensating the transition occurring after the current bit.
10. A method as defined in claim 9 , wherein compensating the current bit such that the transition occurring after the current bit is compensated in the data stream further comprises delaying the data stream in a pulse shaper.
11. A method as defined in claim 9 , wherein compensating the current bit such that the transition occurring after the current bit is compensated in the data stream further comprises advancing the current transition.
12. A method as defined in claim 9 , wherein pre-compensating the current bit such that the current transition is compensated in the data stream further comprises delaying the current transition.
13. A circuit for compensating a transition in a data stream to account for laser jitter, the circuit comprising:
a first delay element in series with a second delay element, wherein the first delay element delays a data stream by a first amount and the second delay element delays the data stream by a second amount;
a first logic gate connected to the first delay element and the second delay element such that an output of the first logic gate is high when a falling transition is occurs in the data stream;
a second logic gate connected to the first delay element and the second delay element such that an output of the second logic gate is high when a rising transition occurs in the data stream;
a gain circuit connected to the first logic gate and the second logic gate that provides a gain depending at least on whether a rising or falling transition is detected in the data stream; and
a pulse shaper that delays the data stream such that the gain of the weighting element is summed with the data stream prior to transitions detected by the first logic gate and the second logic gate such that the transitions are either advanced or delayed.
14. A circuit as defined in claim 13 , wherein the first delay element includes a plurality of buffers and the second delay element includes a plurality of buffers.
15. A circuit as defined in claim 13 , wherein the first logic gate is an AND gate having an inverted output of the first delay element and an output of the second delay element as inputs.
16. A circuit as defined in claim 13 , wherein the second logic gate is an AND gate having an inverted output of the second delay element and an output of the first delay element as inputs.
17. A circuit as defined in claim 13 , wherein the pulse shaper includes a plurality of buffers.
18. A circuit as defined in claim 13 , wherein the gain circuit includes an input for negative gain, an input for positive gain, an input for polarity down and an input for polarity up.
19. A circuit as defined in claim 13 , further comprising a summer for summing the gain of the gain circuit with an output of the pulse shaper such that a bit following each detected transition is peaked either such that a transition following each detected transition is compensated.
20. A circuit as defined in claim 19 , wherein a particular bit is peaked positively to delay a transition following the particular bit if the detected transition was a rising transition, and wherein the particular bit is peaked negatively to advance a transition following the particular bit if the detected transition was a rising transition.
21. A circuit as defined in claim 19 , wherein a particular bit is peaked negatively to delay a transition following the particular bit if the detected transition was a falling transition, and wherein the particular bit is peaked positively to advance a transition following the particular bit if the detected transition was a falling transition.