Logical circuit

1. A logical circuit which receives first and second input signals in which a period of a first logic level partially overlaps, and outputs first and second output signals in which a period of the first logic level does not overlap, the logical circuit comprising:

a first unit changing a phase of the first output signal from a second logic level to the first logic level when a change of the first input signal from the second logic level to the first logic level is detected; and

a second unit changing a phase of the second output signal from the first logic level to the second logic level when the second input signal is detected as being at the first logic level at a time of detection of the change of the first input signal.

2. A logical circuit according to claim 1 wherein the phase of the second output signal is changed from the second logic level to the first logic level when a change of the second input signal from the second logic level to the first logic level is detected, and the phase of the first output signal is changed from the first logic level to the second logic level when a chance of the first input signal from the first logic level to the second logic level is detected.

3. A logical circuit according to claim 1 wherein the logical circuit comprises:

a first output unit which outputs the first output signal;

a second output unit which outputs the second output signal;

a first state holding unit which holds, when the phases of the first and second input signals are set to the first logic level simultaneously, a state of the first input signal immediately preceding the setting; and

a second state holding unit which holds, when the phases of the first and second input signals are set to the first logic level simultaneously, a state of the second input signal immediately preceding the setting;

wherein the first output unit outputs the first output signal based on the first input signal and information held in the second state holding unit, and the second output unit outputs the second output signal based on the second input signal and information held in the first state holding unit.

4. A logical circuit according to claim 1 wherein the first and second input signals are two clock signals with mutually shifted phases.

5. A semiconductor device comprising:

a logical circuit which receives first and second input clock signals in which a period of a first logic level partially overlaps, and outputs first and second output clock signals in which a period of the first logic level does not overlap; and

a parallel-serial conversion circuit which receives first and second data in parallel and outputs the first and second data serially, the first and second output clock signals from the logical circuit are transmitted to the parallel-serial conversion circuit as clock signals,

wherein the logical circuit comprises:

a first unit changing a phase of the first output clock signal from a second logic level to the first logic level when a change of the first input clock signal from the second logic level to the first logic level is detected; and

a second unit changing a phase of the second output clock signal from the first logic level to the second logic level when the second input clock signal is detected as being at the first logic level at a time of detection of the change of the first input clock signal.

6. A semiconductor device according to claim 5 wherein the logical circuit is provided so that the phase of the second output clock signal is changed from the second logic level to the first logic level when a change of the second input clock signal from the second logic level to the first logic level is detected, and the phase of the first output clock signal is changed from the first logic level to the second logic level when a change of the first input signal from the first logic level to the second logic level is detected.

7. A semiconductor device according to claim 5 wherein the logical circuit comprises:

a first output unit which outputs the first output clock signal;

a second output unit which outputs the second output clock signal;

a first state holding unit which holds, when the phases of the first and second input clock signals are set to the first logic level simultaneously, a state of the first input clock signal immediately preceding the setting; and

a second state holding unit which holds, when the phases of the first and second input clock signals are set to the first logic level simultaneously, a state of the second input clock signal immediately preceding the setting;

wherein the first output unit outputs the first output clock signal based on the first input clock signal and information held in the second state holding unit, and the second output unit outputs the second output clock signal based on the second input clock signal and information held in the first state holding unit.