Top drain MOSFET
View Patent ↗A power MOSFET is disclosed in which the source and drain regions are reversed from their usual positions and the drain is on the top of the chip (the surface containing the junction pattern diffusions) and the source is on the bottom of the chip. A plurality of spaced trenches are formed in the top surface. One group of trenches contain gate polysilicon and a gate oxide to control an invertible channel region along the trench. A second group of the trenches have a buried source contact at their bottoms which are connected between the N source material to the P channel region to short out a parasitic bipolar transistor.
1. A mosgated device comprising:
a silicon chip having top and bottom parallel surfaces and including:
a drain region adjacent to said top surface;
a channel region under said drain region; and
a source region under said channel region;
said mosgated device having a drain electrode facing a first direction and a source electrode facing a second direction opposite said first direction, said drain electrode being disposed on said top surface and covering a full surface of said drain region exposed at said top surface, and said source electrode being disposed on said bottom surface, a plurality of parallel trenches formed in said top surface; a first group of said trenches each containing a mosgate electrode having a silicide layer atop thereof to reduce lateral resistance, and extending along said channel region to enable and prevent conduction between said drain and source electrodes, a second group of parallel trenches; each of said second group of trenches having a silicide layer at the bottom thereof which connects said channel region and said source region; and an implant region of the same conductivity as, and doped to a greater concentration than, said source region under each silicide layer.
2. The device of claim 1 , further comprising a plurality of doped implant regions each having a same conductivity type as said source region and each being formed within said source region below a respective one of said conductive regions at the bottom of said second group of trenches, said plurality of doped implant regions ensuring good connection between said channel and source regions.
3. A mosgated device comprising:
a silicon chip having top and bottom parallel surfaces and including:
a drain region adjacent to said top surface;
a channel region under said drain region; and
a source region under said channel region;
a first plurality of trenches formed in said top surface of said silicon chip and each containing a mosgate electrode having a silicide layer atop thereof to reduce lateral resistance and extending along said channel region;
a second plurality of trenches formed in said top surface of said silicon chip and each having a bottom end;
a layer of silicide at the bottom end of each of said second plurality of trenches connecting said source and channel regions;
a doped implant region having a same conductivity type as, and doped to a greater concentration than, said source region formed within said source region below a respective silicide layer, said doped implant regions ensuring good connection between said source and channel regions; and
a drain electrode facing one direction and a source electrode facing another direction opposite said one direction, said drain electrode being disposed on said top surface, and said source electrode being disposed on said bottom surface.
4. The device of claim 3 , wherein said second plurality of trenches are interlaced and spaced from said first plurality of trenches.
5. The device of claim 3 , wherein said drain electrode covers a full surface of said drain region exposed at said top surface.