Rate control in a video encoder according to a bit count estimate
View Patent ↗Described herein is a rate controller in a video system. The rate controller is comprised of a bit count estimator and a quantization selector. The bit count estimator receives an input to an encoder and generates a bit count estimate. The bit count estimate is an approximation of a bit count at an output of the encoder. The quantization selector sets a quantization value based on the bit count estimate.
1. A method for rate control, said method comprising:
generating a bit count estimate based on an input to an encoder, wherein the bit count estimate is an estimate of a bit count at an output of said encoder; and
selecting a quantizer level based on the bit count estimate.
2. The method of claim 1 , wherein the encoder is an arithmetic encoder.
3. The method of claim 1 , wherein the encoder is an entropy encoder.
4. The method of claim 1 , wherein the method further comprises: binarizing one or more symbols, thereby generating the input to the encoder.
5. The method of claim 1 , wherein generating the quantizer level further comprises:
comparing the bit count estimate to an ideal bit count, thereby producing a difference; and
selecting a quantizer value based on the difference.
6. The method of claim 1 , wherein the method further comprises: utilizing the quantizer value in a block processor.
7. A rate controller for video encoding, said rate controller comprising:
a bit count estimator operable to receive an input to an encoder and generating a bit count estimate, wherein the bit count estimate estimates a bit count at an output of said encoder; and
a quantization selector operable to set a quantization value based on the bit count estimate.
8. The rate controller of claim 7 , wherein the encoder is an arithmetic encoder.
9. The rate controller of claim 7 , wherein the encoder is an entropy encoder.
10. The rate controller of claim 7 , wherein the input to the encoder is a binarization of one or more symbols.
11. The rate controller of claim 7 further comprising:
a bit comparator operable to compare the bit count estimate to an ideal bit count, thereby producing a difference; and
a quantization selector operable to select the quantizer value based on the difference.
12. The rate controller of claim 7 , wherein a block processor utilizes the quantizer value.
13. An integrated circuit for controlling bit rate, said integrated circuit comprising:
arithmetic logic operable to receive an input to an encoder and generate a bit count estimate, wherein the bit count estimate approximates a bit count of an output from said encoder; and
memory for storing one or more quantization levels;
wherein the bit count estimate is used to select a quantization level in the one or more quantization levels.
14. The integrated circuit of claim 13 , wherein the encoder is an arithmetic encoder.
15. The integrated circuit of claim 13 , wherein the encoder is an entropy encoder.
16. The integrated circuit of claim 13 , wherein the input to the encoder is a binarization of one or more symbols.
17. The integrated circuit of claim 13 , wherein the arithmetic logic is further operable:
to compare the bit count estimate to an ideal bit count, thereby producing a difference, wherein the quantizer value is based on said difference.
18. The integrated circuit of claim 13 , wherein a block processor utilizes the quantizer value.