Programmable logic cells with local connections
A programmable logic structure is disclosed employing input logic routing cell (ILRC) multiplexers and output logic routing cell (OLRC) multiplexers for making local connections between dedicated logic cells. In a simple programmable logic structure, a dedicated logic cell (DLC) is implemented in a programmable logic structure comprising multiple ILRC multiplexers for port A and multiple OLRC multiplexers for port B. In a multi-level programmable logic structure, multiple columns of dedicated logic cells is designed with columns of dedicated local cells adjacent to each other where each DLC column is used to implement a particular logic function. In a first embodiment, local connections can be made between dedicated logic cells, e.g. an OLRC in a first DLC at level L making local point-to-point connections to an ILRC in a second DLC at level L+1. In a second embodiment, local connections can be made from any other dedicated logic cells, whether positioned horizontally or vertically relative to a relative point or multiplexer, and from any offset from a current logic and routing cell (LRC). In a third embodiment, local connections can be made by stitching a first OLRC to a second OLRC (for connecting to an ILRC), which allows lines from other columns or levels of DLC to reach an ILRC for a fast local interconnect.
1. A programmable logic structure for point-to-point local connections, comprising
an output logic and routing cell multiplexer in a first means at a first level; and
a first input logic and routing cell multiplexer in a second dedicated logic at a second level, the output logic and routing cell multiplexer in the first dedicated logic cell at the first level making a direct point-to-point connection to the first input logic and routing multiplexer cell in the second dedicated logic cell at the second level without routing the connection through a switch circuit;
wherein the first dedicated logic cell comprises;
a first logic and routing cell; and
a second logic and routing cell coupled to the first logic and routing cell, the first logic and routing cells including:
a first look-up table having a plurality of inputs for receiving a set of inputs and at least one output;
a second look-up table having a plurality of inputs for receiving the set of inputs and at least one output;
a third look-up table for receiving at least one input and generating at least one output; and
a fourth-look-up table for receiving at least one input and generating at least one output;
a logic having inputs coupled to the first, second, third, fourth look-up tables and generating at least one output.
2. The programmable logic structure of claim 1 , wherein the first level to the second level point-to-point connection comprises L to L+1 point-to-point connection; and wherein the first dedicated logic cell at the first level is symmetric to the second dedicated logic cell at the second level.
3. The programmable logic structure of claim 1 , wherein the first level to the second level point-to-point connection comprises L to L−n, where n is a positive integer number; and wherein the first dedicated logic cell at the first level is symmetric to the second dedicated logic cell at the second level.
4. The programmable logic structure of claim 1 , wherein the first level to the second level point-to-point connection comprises L to L+n that denotes a horizontal offset, where n is a positive integer number; and wherein the first dedicated logic cell at the first level is symmetric to the second dedicated logic cell at the second level.
5. The programmable logic structure of claim 1 , wherein the first level to the second level point-to-point connection comprises M to M+n that denotes a vertical offset, where n is a positive integer number; and wherein the first dedicated logic cell at the first level is symmetric to the second dedicated logic cell at the second level.
6. The programmable logic structure of claim 1 , wherein the programmable logic structure produces fan out point-to-point connections by coupling the output logic and routing cell multiplexer commonly to the first input logic and routing cell multiplexer and a second input logic and routing cell multiplexer.
7. The programmable logic structure of claim 1 , further comprises a buffer that couples between the output logic and routing cell multiplexer in the first dedicated logic cell at the first level and the first input logic and routing cell multiplexer in the second dedicated logic cell in the second level, the buffer comprising an inverter buffer or a non-inverting buffer.
8. The programmable logic structure of claim 1 , wherein the first dedicated logic cell resides in a logic and routing block, the logic and routing block including one or more dedicated logic cells.
9. A method for programming a programmable logic circuit, comprising:
providing a first dedicated logic cell and a second dedicated logic cell, the first dedicated logic cell having a first output logic and routing cell multiplexer with an input, the second dedicated logic cell having a second output logic and routing cell multiplexer with an output; and
stitching the output of the second output logic and routing cell multiplexer in the second dedicated logic cell to the input of the first output logic and routing cell multiplexer in the first dedicated logic cell by making a direct point-to-point connection between the output of the second output logic and routing cell and the input of the first output logic and routing cell without routing the connection through a switch circuit;
wherein the first dedicated logic cell comprises:
a first logic and routing cell and
a second logic and routing cell coupled to the first logic and routing cell, the first logic and routing cells including:
a first look-up table having a plurality of inputs for receiving a set of inputs and at least one output;
a second look-up table having a plurality of inputs for receiving the set of inputs and at least one output;
a third look-up table for receiving at least one input and generating at least one output; and
a fourth-look-up table for receiving at least one input and generating at least one output;
a logic having inputs coupled to the first, second, third, fourth look-up tables and generating at least one output.
10. The method of claim 9 , further comprising stitching a third OLRC multiplexer to a second input of the first OLRC multiplexer through a local connection.
11. The method of claim 10 , wherein the first OLRC multiplexer and the second OLRC multiplexer reside in the same level of dedicated logic cells.
12. The method of claim 10 , wherein the first OLRC multiplexer resides in a different level of dedicated logic cells than the second OLRC multiplexer.