Semiconductor devices employing at least one modulation doped quantum well structure and one or more etch stop layers for accurate contact formation
View Patent ↗A semiconductor device includes a series of layers formed on a substrate, the layers including a first plurality of layers including an n-type ohmic contact layer, a p-type modulation doped quantum well structure, an n-type modulation doped quantum well structure, and a fourth plurality of layers including a p-type ohmic contact layer. Etch stop layers are used to form contacts to the n-type ohmic contact layer and contacts to the n-type modulation doped quantum well structure. Thin capping layers are also provided to protect certain layers from oxidation. Preferably, each such etch stop layer is made sufficiently thin to permit current tunneling therethrough during operation of optoelectronic/electronic devices realized from this structure (including heterojunction thyristor devices, n-channel HFET devices, p-channel HFET devices, p-type quantum-well-base bipolar transistor devices, and n-type quantum-well-base bipolar transistor devices). In another aspect of the present invention, a high performance bipolar transistor device is realized from this structure by implanting p-type ions in a interdigitization pattern that forms a plurality of p-type ion implant regions on both sides of the p-type modulation doped quantum well structure to a depth that penetrates the n-type ohmic contact layer. The interdigitization pattern of the p-type implants reduces capacitance between the p-type modulation doped quantum well structure and the n-type ohmic contact layer to enable higher frequency operation.
1. A transistor device comprising:
a series of layers formed on a substrate, said layers including a first plurality of layers comprising n-type dopant material, a second plurality of layers formed above said first plurality of layers and including a p-type modulation doped quantum well structure that defines a channel region, and a third plurality of layers formed above said second plurality of layers and comprising n-type dopant material, wherein said first plurality of layers includes an n-type ohmic contact layer;
a collector terminal metal layer that is formed above said third plurality layers, said collector terminal metal layer having a first side opposite a second side;
a plurality of p-type ion implant regions that are disposed on said first and second sides of said collector terminal metal layer, said p-type ion implant regions operably coupled to said channel region defined by said p-type modulation doped quantum well structure;
a patterned base terminal metal layer that is formed on said said p-type ion implant regions for contact to said channel region defined by said p-type modulation doped quantum well structure; and
a patterned emitter terminal metal layer that is formed on said n-type ohmic contact layer on said first and second sides of said collector terminal metal layer;
wherein said patterned base terminal metal layer is interdigitated with respect to said patterned emitter terminal layer on both said first and second sides of said collector terminal metal layer.
2. A transistor device according to claim 1 , wherein:
said plurality of p-type ion implant regions reduce capacitance between said p-type modulation doped quantum well structure and said n-type ohmic contact layer.
3. A transistor device according to claim 1 , wherein:
wherein said first plurality of layers includes a first etch stop layer for contacting said n-type ohmic contact layer.
4. A transistor device according to claim 3 , wherein:
said first etch stop layer is sufficiently thin to permit current tunneling.
5. A transistor device according to claim 1 , wherein:
said third plurality of layers comprise an n-type implant region formed below said collector terminal metal layer.
6. A transistor device according to claim 1 , wherein:
said third plurality of layers form an n-type modulation doped quantum well structure.
7. A transistor device according to claim 1 , further comprising:
a first plurality of undoped spacer layers disposed between said first plurality of layers and said second plurality of layers; and
a second plurality of undoped spacer layers disposed between said second plurality of layers and said third plurality of layers; and
wherein said first plurality of undoped spacer layers include a thin capping layer.
8. A transistor device according to claim 1 , wherein:
said second plurality of layers comprise at least one layer of undoped InGaAsN and at least one layer of undoped GaAs that form at least one quantum well.
9. A transistor device according to claim 1 , wherein:
said second plurality of layers comprise at least one layer of AlGaAs of high p-type doping concentration to form a modulation doped layer for said at least one quantum well.
10. A transistor device according to claim 3 , wherein:
said first etch stop layer comprises AIAs that functions as an etch stop during etching by a chlorine-based gas mixture that includes fluorine.
11. A transistor device according to claim 1 , wherein:
said series of layers comprises group III-V materials.
12. A transistor device according to claim 1 , further comprising:
at least one undoped spacer layer disposed between said first plurality of layers and said second plurality of layers; and
at least one undoped spacer layers disposed between said second plurality of layers and said third plurality of layers.
13. A transistor device according to claim 1 , further comprising:
a first plurality of undoped spacer layers disposed between said first plurality of layers and said second plurality of layers; and
a second plurality of undoped spacer layers disposed between said first plurality of layers and said second plurality of layers,;
wherein at least one of said first and second plurality of undoped spacers layers comprise layers of different materials.