IP Library Granted Patent US 7,554,159
Granted Patent B2
US 7,554,159 · App. 11/045,300 · Granted Jun 30, 2009

Electrostatic discharge protection device and method of manufacturing the same

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Quick Facts
Patent No.
US 7,554,159
App. No.
11/045,300
Granted
Jun 30, 2009
Kind
B2
Abstract

An electrostatic discharge protection device that includes a semiconductor substrate of a first dopant type, at least one source/drain pair of a second dopant type formed in the substrate, wherein the source/drain pair is separated to define a channel region therebetween, a lightly-doped region of the first dopant type defined between the source/drain pair and including at least a portion of the channel region, a gate dielectric layer formed over the substrate, and a gate formed over the gate dielectric layer and above the channel region.

Claims (53)

1. A method, comprising:

providing a semiconductor substrate of a first dopant type;

forming a well region of the first dopant type in the substrate;

forming a lightly doped region of the first dopant type in the well region;

forming at least one source/drain pair of a second dopant type in the substrate, wherein a source region of the source/drain pair is separated from a drain region of the source/drain pair by a channel region;

forming a gate on the substrate and over both the channel region and the lightly doped region so that the lightly doped region is directly below a central portion of the gate;

forming lightly doped drain (LDD) regions of the second dopant type adjacent to the gate;

forming a first diffused region of the second dopant type under the drain region of the source/drain pair; and

forming a second diffused region of the second dopant type under the source region of the source/drain pair.

2. The method of claim 1 , wherein the gate is formed over the well region of the first dopant type.

3. The method of claim 1 , further comprising forming a sidewall spacer adjacent to the gate and over the LDD regions.

4. The method of claim 1 , wherein the first dopant type comprises a p-type dopant, and wherein the second dopant type comprises an n-type dopant.

5. The method of claim 1 , wherein the lightly doped region is formed to be contiguous with both the source region and the drain region.

6. The method of claim 1 , wherein the first and second diffused regions extend into a portion of the LDD regions.

7. The method of claim 6 , further comprising forming pocket regions of the first dopant type adjacent to the source and drain regions and below the LDD regions.

8. The method of claim 7 , wherein the lightly doped region is formed to be contiguous with the source region and the drain region through the pocket regions.

9. A method, comprising:

providing a semiconductor substrate of a first dopant type;

forming at least one source/drain pair of a second dopant type in the substrate, wherein a source region of the source/drain pair is separated from a drain region of the source/drain pair by a channel region;

forming a gate on the substrate and over the channel region;

forming lightly doped drain (LDD) regions of the second dopant type adjacent to the gate;

forming a first diffused region of the second dopant type under the drain region of the source/drain pair;

forming a second diffused region of the second dopant type under the source region of the source/drain pair; and

forming a third diffused region of the second dopant type under the first diffused region.

10. The method of claim 9 , further comprising forming a sidewall spacer adjacent to the gate and over the LDD regions.

11. The method of claim 9 , wherein the first dopant type comprises a p-type dopant, and wherein the second dopant type comprises an n-type dopant.

12. The method of claim 9 , wherein the first and second diffused regions extend into a portion of the LDD regions.

13. The method of claim 9 , further comprising forming pocket regions of the first dopant type adjacent to the source and drain regions and below the LDD regions.

14. The method of claim 13 , wherein the first and second diffused regions extend into a portion of the LDD regions and the pocket regions.

15. The method of claim 9 , further comprising:

forming isolation regions adjacent to the source and drain regions; and

forming doped regions of the first dopant type adjacent to the source and drain regions.

16. The method of claim 9 , further comprising:

forming a third diffused region of the second dopant type under the first diffused regions; and

forming a fourth diffused region of the second dopant type under the second diffused region.

17. A method, comprising:

providing a semiconductor substrate of a first dopant type;

forming at least one source/drain pair of a second dopant type in the substrate, wherein a source region of the source/drain pair is separated from a drain region of the source/drain pair by a channel region;

forming a gate on the substrate and over the channel region;

forming pocket regions of the first dopant type adjacent to the source and drain regions in the channel region;

forming a first diffused region of the second dopant type under the drain region of the source/drain pair;

forming a second diffused region of the second dopant type under the source region of the source/drain pair; and

forming a third diffused region of the second dopant type under the first diffused region;

wherein a region under the second diffused region is a portion of the substrate having the first dopant type.

18. The method of claim 17 , further comprising forming lightly doped drain (LDD) regions of the second dopant type adjacent to the gate.

19. The method of claim 18 , further comprising forming a sidewall spacer adjacent to the gate and over the LDD regions.

20. The method of claim 18 , wherein the first and second diffused regions extend into a portion of the LDD regions.

21. The method of claim 18 , wherein the pocket regions are below the LDD regions.

22. The method of claim 21 , wherein the first and second diffused regions extend into a portion of the LDD regions and the pocket regions.

23. The method of claim 17 , wherein the first dopant type comprises a p-type dopant, and wherein the second dopant type comprises an n-type dopant.

24. The method of claim 17 , further comprising:

forming isolation regions adjacent to the source and drain regions; and

forming doped regions of the first dopant type adjacent to the source and drain regions.

Assignments (6)
CORRECTIVE ASSIGNMENT TO ADD FIFTH ASSIGNOR PREVIOUSLY RECORDED ON REEL 018910 FRAME 0288. Recorded Jul 22, 2011
From: KER, MING-DOU; TSENG, TANG-KUI; JIANG, HSIN-CHIN; CHANG, CHYH-YIH; PENG, JENG-JIE
To: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Reel/Frame 026633/0750 →
CORRECTIVE ASSIGNMENT, REEL FRAME #018721/0332, EXECUTION DATE 11/15/2006 Recorded Aug 20, 2007
From: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
To: TRANSPACIFIC IP, LTD.
Reel/Frame 019719/0099 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2007
From: KER, MING-DOU; TSENG, TANG-KUI; JIANG, HSIN-CHIN; CHANG, CHYH-YIH; PENG, JENG-JIE
To: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Reel/Frame 018910/0288 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2007
From: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
To: TRANSPACIFIC IP LTD.
Reel/Frame 018910/0324 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 3, 2007
From: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
To: TRANSPACIFIC IP, LTD.
Reel/Frame 018721/0332 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 17, 2006
From: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
To: TRANSPACIFIC IP LTD.
Reel/Frame 018532/0085 →