Low-power memory write circuits
View Patent ↗One embodiment of the present invention provides a system that writes to a cell in a memory using a low-voltage-swing signal across a pair of global bit-lines. During operation, the system receives a low-voltage-swing signal across a pair of global bit-lines, which is too low to reliably write the memory cell. Next, the system converts the low-voltage-swing signal to a high-voltage-swing signal, which is adequate to reliably write the memory cell. The system then writes to the memory cell by applying the high-voltage-swing signal across a pair of local bit-lines that are coupled to the memory cell. The use of low-voltage-swing signals on the global bit-lines reduces overall power consumption. Furthermore, in one embodiment of the present invention, the voltage conversion is achieved using a pair of cross-coupled NMOS transistors whose sources are directly or indirectly coupled with the global bit-lines, and whose drains are directly or indirectly coupled with the local bit-lines.
1. A method for writing to a cell in a memory using a low-voltage-swing signal across a pair of global bit-lines, the method comprising:
receiving a low-voltage-swing signal across a pair of global bit-lines;
converting the low-voltage-swing signal to a high-voltage-swing signal; and
writing to the cell in the memory by applying the high-voltage-swing signal across a pair of local bit-lines coupled to the cell in the memory;
wherein using a low-voltage-swing signal instead of a high-voltage-swing signal across the pair of long and high-capacitance global bit-lines reduces the overall power consumption of the memory.
2. The method of claim 1 , wherein converting the low-voltage-swing signal to a high-voltage-swing signal involves using a first pair of cross-coupled NMOS(N-channel Metal-Oxide-Semiconductor) transistors.
3. The method of claim 2 , wherein the respective sources of the first pair of cross-coupled NMOS transistors are directly or indirectly coupled to the respective global bit-lines, and wherein the respective drains of the first pair of cross-coupled NMOS transistors are directly or indirectly coupled to the respective local bit-lines.
4. The method of claim 3 , wherein the direct or indirect coupling of the sources of the first pair of cross-coupled NMOS transistors to the global bit-lines is facilitated using a pair of selection transistors having a common gate voltage.
5. The method of claim 4 , wherein converting the low-voltage-swing signal to the high-voltage-swing signal involves using a second pair of cross-coupled NMOS transistors to quickly discharge a local bit-line in the pair of local bit-lines, thereby quickly creating the high-voltage-swing signal across the pair of local bit-lines.
6. The method of claim 1 , wherein a global bit-line in the pair of global bit-lines is coupled to a plurality of intermediate bit-lines.
7. The method of claim 6 , wherein an intermediate bit-line in a pair of intermediate bit-lines is coupled to a plurality of local bit-lines.
8. An apparatus for writing to a cell in a memory using a low-voltage-swing signal across a pair of global bit-lines, the apparatus comprising:
a receiving mechanism configured to receive a low-voltage-swing signal across a pair of global bit-lines;
a converting mechanism configured to convert the low-voltage-swing signal to a high-voltage-swing signal; and
a writing mechanism configured to write to the cell in the memory by applying the high-voltage-swing signal across a pair of local bit-lines coupled to the cell in the memory;
wherein using the low-voltage-swing signal instead of the high-voltage-swing signal across the pair of long and high-capacitance global bit-lines reduces the overall power consumption of the memory.
9. The apparatus of claim 8 , wherein the converting mechanism includes a first pair of cross-coupled NMOS(N-channel Metal-Oxide-Semiconductor) transistors.
10. The apparatus of claim 9 , wherein the respective sources of the first pair of cross-coupled NMOS transistors are directly or indirectly coupled to the respective global bit-lines, and wherein the respective drains of the first pair of cross-coupled NMOS transistors are directly or indirectly coupled to the respective local bit-lines.
11. The apparatus of claim 10 , wherein the direct or indirect coupling of the sources of the first pair of cross-coupled NMOS transistors to the global bit-lines is facilitated using a pair of selection transistors having a common gate voltage.
12. The method of claim 11 , wherein the converting mechanism includes a second pair of cross-coupled NMOS transistors to quickly discharge a local bit-line in the pair of local bit-lines, thereby quickly creating the high-voltage-swing signal across the pair of local bit-lines.
13. The apparatus of claim 8 , wherein a global bit-line in the pair of global bit-lines is coupled to a plurality of intermediate bit-lines.
14. The apparatus of claim 13 , wherein an intermediate bit-line in a pair of intermediate bit-lines is coupled to a plurality of local bit-lines.
15. A computer system that includes a circuit for writing to a cell in a memory using a low-voltage-swing signal across a pair of global bit-lines, the circuit comprising:
a receiving-circuit configured to receive a low-voltage-swing signal across a pair of global bit-lines;
a converting-circuit configured to convert the low-voltage-swing signal to a high-voltage-swing signal; and
a writing-circuit configured to write to the cell in the memory by applying the high-voltage-swing signal across a pair of local bit-lines coupled to the cell in the memory;
wherein using the low-voltage-swing signal instead of the high-voltage-swing signal across the pair of long and high-capacitance global bit-lines reduces the overall power consumption of the memory.
16. The computer system of claim 15 , wherein the converting-circuit includes a first pair of cross-coupled NMOS(N-channel Metal-Oxide-Semiconductor) transistors.
17. The computer system of claim 16 , wherein the respective sources of the first pair of cross-coupled NMOS transistors are directly or indirectly coupled to the respective global bit-lines, and wherein the respective drains of the first pair of cross-coupled NMOS transistors are directly or indirectly coupled to the respective local bit-lines.
18. The computer system of claim 17 , wherein the direct or indirect coupling of the sources of the first pair of cross-coupled NMOS transistors to the global bit-lines is facilitated using a pair of selection transistors having a common gate voltage.
19. The computer system of claim 18 , wherein the converting-circuit includes a second pair of cross-coupled NMOS transistors to quickly discharge a local bit-line in the pair of local bit-lines, thereby quickly creating the high-voltage-swing signal across the pair of local bit-lines.
20. The computer system of claim 15 , wherein a global bit-line in the pair of global bit-lines is coupled to a plurality of intermediate bit-lines.
21. The computer system of claim 20 , wherein an intermediate bit-line in a pair of intermediate bit-lines is coupled to a plurality of local bit-lines.