Mechanism for processing speculative LL and SC instructions in a pipelined processor
View Patent ↗A processor includes a first circuit and a second circuit. The first circuit is configured to provide a first indication of whether or not at least one reservation is valid in the processor. A reservation is established responsive to processing a load-linked instruction, which is a load instruction that is architecturally defined to establish the reservation. A valid reservation is indicative that one or more bytes indicated by the target address of the load-linked instruction have not been updated since the reservation was established. The second circuit is coupled to receive the first indication. Responsive to the first indication indicating no valid reservation, the first circuit is configured to select a speculative load-linked instruction for issued. The second circuit is configured not to select the speculative load-linked instruction for issue responsive to the first indication indicating the at least one valid reservation. A method is also contemplated.
1. A method comprising:
commencing to issue a load-linked instruction;
determining if the load-linked instruction is a speculative instruction;
issuing the load-linked instruction if it is not a speculative instruction;
determining for a speculative load-linked instruction, if a valid reservation is currently being maintained for a target address of another load-linked instruction, wherein the speculative load-linked instruction is not issued when a valid reservation is currently being maintained;
determining for the speculative load-linked instruction that has no valid reservation currently being maintained, if another load-linked instruction is currently in a processing pipeline; and
issuing the speculative load-linked instruction if no valid reservation is currently being maintained and not another load-linked instruction is currently in the processing pipeline.
2. The method of claim 1 wherein a valid reservation is determined by determining a state of a load-linked set bit.
3. The method of claim 1 wherein determining if another load-linked instruction is in the processing pipeline is achieved by identifying pipe states and type fields in an issue queue.
4. The method of claim 1 wherein determining if another load-linked instruction is in the processing pipeline is achieved by receiving information from a load/store pipeline.
5. The method of claim 2 wherein the load-linked set bit is used to indicate a valid reservation in one or more of a plurality of reservation registers.