Thin film oxide interface
View Patent ↗An oxide interface and a method for fabricating an oxide interface are provided. The method comprises forming a silicon layer and an oxide layer overlying the silicon layer. The oxide layer is formed at a temperature of less than 400° C. using an inductively coupled plasma source. In some aspects of the method, the oxide layer is more than 20 nanometers (nm) thick and has a refractive index between 1.45 and 1.47. In some aspects of the method, the oxide layer is formed by plasma oxidizing the silicon layer, producing plasma oxide at a rate of up to approximately 4.4 nm per minute (after one minute). In some aspects of the method, a high-density plasma enhanced chemical vapor deposition (HD-PECVD) process is used to form the oxide layer. In some aspects of the method, the silicon and oxide layers are incorporated into a thin film transistor.
1. An oxide interface comprising:
a transparent substrate;
a silicon layer overlying the substrate;
an oxide layer, with a thickness of more than 20 nanometers (nm) and a refractive index between approximately 1.45 and 1.47, overlying the silicon layer; and,
wherein the oxide layer is an oxide bilayer having a thickness of up to 100 nm, with a first sub-layer of oxide overlying the silicon layer and a second sub-layer of oxide overlying the first oxide sub-layer.
2. The oxide interface of claim 1 wherein the oxide interface layer has a thickness up to 100 nm.
3. The oxide interface of claim 1 wherein the silicon layer is selected from the group including amorphous silicon, microcrystalline silicon, and polycrystalline silicon.
4. The oxide interface of claim 1 wherein the oxide layer is selected from the group consisting of silicon oxide and silicon oxynitride.
5. The oxide interface of claim 1 further comprising:
a diffusion barrier overlying the substrate and underlying the silicon layer; and,
a gate electrode overlying the oxide layer; and
wherein the silicon layer includes channel, source, and drain regions; and,
wherein the oxide layer has a fixed oxide charge density of less than 5×10 11 per square centimeter.
6. The oxide interface of claim 5 wherein the oxide layer has:
an interface trap concentration of approximately 0.9×10 10 to 8×10 10 per square centimeter−electron volt (/cm 2 eV);
a flat band voltage shift of less than 1 V under a 30 minute bias temperature stress reliability test at 150° C. and ±2 megavolts per centimeter (MV/cm);
a leakage current density lower than 10 −7 amperes per square centimeter (A/cm 2 ) at an applied electric field of 8 MV/cm; and,
a breakdown field strength greater than 10 MV/cm.
7. A thin film transistor (TFT) comprising:
a transparent substrate;
a diffusion barrier overlying the transparent substrate;
a silicon layer with channel, source, and drain regions overlying the diffusion barrier;
an oxide gate insulator layer with a fixed oxide charge density of less than 5×10 11 per square centimeter overlying the silicon layer; and,
a gate electrode overlying the oxide gate insulator layer.
8. The TFT of claim 7 wherein the oxide gate insulator layer has a thickness of less than 20 nanometers (nm).
9. The TFT of claim 7 wherein the oxide gate insulator layer has a thickness between 10 and 100 nm.
10. The TFT of claim 7 wherein the oxide gate insulator layer has:
a first sub-layer of oxide overlying the silicon layer and a second sub-layer of oxide overlying the first sub-layer; and,
a thickness between 10 and 100 nanometers.