ASICs having programmable bypass of design faults
View Patent ↗A relatively small amount of programmable or reprogrammable logic (pro-Logic) is included in a mostly-ASIC device so that such re/programmable logic can be used as a substitute for, or for bypassing a fault-infected ASIC block (if any) either permanently or at times when the fault-infected ASIC block is about to perform a fault-infected operation (bug-infected operation). The substitution or bypass does not have to be a permanent one that is in effect at all times for the entirety of the fault-infected ASIC block. Instead affected outputs of the faulty ASIC block can be disabled from working just at the time they would otherwise initiate or propagate an error. Such fault-infected operations of the temporarily deactivated ASIC block(s) may be substituted for by appropriately programmed pro-Logic at the appropriate times. Thus, a fault-infected ASIC block that is 99% good (for example) and operates improperly just 1% of the time can continue to be gainfully used for that 99% of the time when its operations are fault free and can be blocked from having its erroneous output(s) used only in the 1% time periods (example) when its behavior is faulty. During those faulty times, a relatively small amount of the pro-Logic can be used as a fault-correcting or fault-bypassing substitute for the fault-infected ASIC block. This substitution or bypassing can be activated after initial design of the mostly-ASIC circuitry and/or after pilot production and/or mass production thereby providing for cost saving and faster time to market and/or for repair or maintenance even years after installation and use of the mostly-ASIC device.
1. A hybrid-ASIC having a given amount of circuit space and comprising:
a substantially non-programmable ASIC logic portion (np-Logic portion); and
a substantially programmable logic portion (pro-Logic portion),
wherein:
the pro-Logic portion includes programmable intervention realizing means operatively coupled for intervening with operations of the np-Logic portion;
the pro-Logic portion includes programmable intervention determining means for determining when, if at all, to intervene with operations of the np-Logic portion;
said intervention determining means recognizes intervention-deserving events;
said intervention determining means is coupled to the intervention realizing means;
the np-Logic portion comprises a plurality of standard cell blocks operatively intercoupled by way of interconnect means;
said programmable intervention realizing means is operatively coupled to said interconnect means for intervening with operations of the np-Logic portion in response to intervention-deserving events recognized by said intervention determining means; and
the programmable intervention determining means is operatively coupled to said interconnect means for detecting states of the np-Logic portion and thereby determining when to signal the intervention realizing means to intervene with operations of the np-Logic portion.
2. A hybrid-ASIC having a given amount of circuit space and comprising:
a substantially non-programmable ASIC logic portion (np-Logic portion); and
a substantially programmable logic portion (pro-Logic portion),
wherein:
the pro-Logic portion includes programmable intervention realizing means operatively coupled for intervening with operations of the np-Logic portion;
the pro-Logic portion includes programmable intervention determining means for determining when, if at all, to intervene with operations of the np-Logic portion;
said programmable intervention realizing means includes ASIC-block activating/de-activating means for selectively activating or deactivating respective non-programmable ASIC blocks in said np-Logic portion and where said ASIC-block activating/de-activating means is comprised of at least one of:
selectively blowable fuses;
selectively close-able anti-fuses;
one-time-programmable memory (OTP);
electrically re-programmable nonvolatile memory;
magnetically re-programmable nonvolatile memory;
optically re-programmable nonvolatile memory;
magneto-optically re-programmable nonvolatile memory; and
volatile DRAM, SRAM or other memory devices whose storage data can be downloaded from other non-volatile memory devices external to said hybrid ASIC before operational use is made of the hybrid ASIC.
3. The hybrid-ASIC of claim 2 wherein:
said ASIC-block activating/de-activating means is operatively coupled to selectively actuate switches among at least one of:
power providing switches which provide power selectively to a corresponding one or more of said ASIC blocks; and
exterior coupling switches which provide coupling selectively between a corresponding plurality of to-exterior linking nodes or pins and a corresponding one or more of said ASIC blocks.