High density FET with self-aligned source atop the trench
View Patent ↗A method for manufacturing a power semiconductor device which includes forming a semiconductor region such as a polysilicon layer or epitaxially grown silicon over a region implanted with source implants and applying heat in a thermal step to cause the source implants to diffuse into the semiconductor region.
1. A process for manufacturing a power semiconductor device comprising:
forming trenches in a semiconductor body of a first conductivity;
forming a channel region of a second conductivity in said semiconductor body;
forming gate structures in said trenches, each gate structure including an insulation layer on top thereof;
implanting dopants of said first conductivity in said insulation layer on top of said gate structures;
forming a semiconductor layer over said trenches in connection with said insulation layer on top of said gate structures;
applying a thermal step to diffuse said dopants of said first conductivity into said semiconductor layer to form conductive regions of said first conductivity; and
forming a metal contact layer over said conductive regions.
2. A process according to claim 1 , wherein said semiconductor layer is comprised of polysilicon.
3. A process according to claim 1 , wherein said semiconductor layer is epitaxially grown silicon.
4. A process according to claim 1 , wherein said gate structures comprise polysilicon.
5. A process according to claim 1 , wherein said semiconductor layer extends over said trenches and said semiconductor body.
6. A process according to claim 1 , wherein said semiconductor layer is of said second conductivity.
7. A process according to claim 6 , wherein said semiconductor body is epitaxially grown silicon, which is grown over a semiconductor substrate of the same conductivity.
8. A process according to claim 7 , further comprising forming another metal contact on said substrate.
9. A process according to claim 8 , wherein said another metal contact is a drain contact, said metal contact layer is a source contact and said conductive regions of said first conductivity are source regions.
10. A process for manufacturing a power semiconductor device comprising:
forming trenches in a silicon body of a first conductivity;
forming a channel region of a second conductivity in said silicon body;
forming gate structures in said trenches, each gate structure including an insulation body atop thereof;
implanting dopants of said first conductivity in each said insulation body;
forming a semiconductor layer over said trenches in contact with said insulation body;
applying a thermal step to diffuse said dopants of said first conductivity into said semiconductor layer to form source regions of said first conductivity; and
forming a source contact over said source regions.
11. A process according to claim 10 , wherein said semiconductor layer is comprised of polysilicon.
12. A process according to claim 10 , wherein said semiconductor layer is epitaxially grown silicon.
13. A process according to claim 10 , wherein said gate structures comprise polysilicon.
14. A process according to claim 13 , wherein said semiconductor layer extends over said trenches.
15. A process according to claim 10 , wherein said silicon body is grown over a silicon substrate of the same conductivity.
16. A process according to claim 15 , further comprising forming a drain contact on said substrate.
17. A process according to claim 15 , wherein said semiconductor layer is of said second conductivity.
18. A process according to claim 15 , further comprising implanting said semiconductor layer with dopants of said second conductivity.