Content addressable memory circuit with improved memory cell stability

1. A content addressable memory (CAM) circuit comprising:

a plurality of memory cells each having an internal node corresponding to one of a mask-true or data-true node and an internal node corresponding to one of a mask-false or data-false node;

a common terminal for the memory cells and operative as a capacitor plate layer common to said memory cells;

a compare circuit operative with the memory cells; and

a capacitor added between the internal nodes of each memory cell corresponding to the mask-true or data-true node and the mask-false or data-false node and the common terminal for memory cell stability.

2. A content addressable memory (CAM) circuit according to claim 1 , wherein said memory cell comprise a Static Random Access Memory (SPAN) circuit.

3. A content addressable memory (CAM) circuit according to claim 1 , and further comprising two series-connected capacitors added between the internal nodes of each memory cell and divided between the common terminal.

4. A content addressable memory (CAM) circuit according to claim 3 , and further comprising a semiconductor layer common to the capacitors.

5. A content addressable memory (CAM) circuit according to claim 1 , wherein said compare circuit comprises two active regions and a plurality of transistors formed over the two active regions.

6. A content addressable memory (CAM) circuit comprising:

first and second memory cells each having an internal node corresponding to one of a mask-true or data-true node and an internal node corresponding to one of a mask-false or data-false node;

a compare circuit operative with the first and second memory cells;

a common terminal for first and second memory cells and operative as a capacitor plate layer common to first and second memory cells; and

a capacitor added between the internal nodes of the memory cells corresponding to the mask-true or data-true node and the mask-false or data-false node and common terminal for memory cell stability.

7. A content addressable memory (CAM) circuit according to claim 6 , wherein said first and second memory cells each comprises Static Random Access Memory (SRAM) circuits.

8. A content addressable memory (CAM) circuit according to claim 6 , and further comprising two series-connected capacitors added between the internal nodes of each of the memory cells and divided between the common terminal.

9. A content addressable memory (CAM) circuit according to claim 8 , and further comprising a semiconductor layer common to the capacitors and common terminal for first and second memory cells.

10. A content addressable memory (CAM) circuit according to claim 6 , wherein said first memory cell is operative for storing a data value and the second memory cell is operative for storing an enable value for enabling the compare circuit.

11. A content addressable memory (CAM) circuit according to claim 6 , wherein said compare circuit comprises two active regions and a plurality of transistors formed over the two active regions.

12. A content addressable memory (CAM) circuit according to claim 6 , and further comprising a polysilicon region forming a local interconnect between the compare circuit and first memory cell.

13. A content addressable memory (CAM) circuit according to claim 6 , and further comprising a polysilicon and conductive region forming a local interconnect between the compare circuit and the second memory cell.

14. A content addressable memory (CAM) circuit according to claim 6 , wherein said common terminal for first and second memory cells has a voltage potential of about one-half the voltage potential for the memory cells.

15. A content addressable memory (CAM) circuit in a semiconductor substrate comprising:

first and second memory cells each having an internal node corresponding to one of a mask-true or data-true node and an internal node corresponding to one of a mask-false or data-false node;

a compare circuit operative with the first and second memory cells;

a common terminal for first and second memory cells and operative as a capacitor plate layer common to said memory cells;

a capacitor added between the internal nodes of the memory cells corresponding to the mask-true or data-true node and the mask-false or data-false node and common terminal for memory cell stability; and

a metallization layer forming word lines and another metallization layer forming bitline and compare lines.

16. A content addressable memory (CAM) circuit according to claim 15 , and further comprising ground lines formed within the metallization layer having the bitline and compare lines.

17. A content addressable memory (CAM) circuit according to claim 15 , wherein said bitline lines comprise bitline true and bitline false lines.

18. A content addressable memory (CAM) circuit according to claim 15 , wherein said compare lines comprise compare true and compare false lines.

19. A content addressable memory (CAM) circuit according to claim 15 , wherein said first and second memory cells each comprises Static Random Access Memory (SRAM) circuits.

20. A content addressable memory (CAM) circuit according to claim 15 , and further comprising two series-connected capacitors added between the internal nodes of each memory cell and divided between the common terminal.

21. A content addressable memory (CAM) circuit according to claim 20 , and further comprising a semiconductor layer common to the capacitors and common terminal for first and second memory cells.

22. A content addressable memory (CAM) circuit according to claim 15 , wherein said first memory cell is operative for storing a data value and the second memory cell is operative for storing an enable value for enabling the compare circuit.

23. A content addressable memory (CAM) circuit according to claim 15 , wherein said compare circuit comprises two active regions and a plurality of transistors formed over the two active regions.

24. A content addressable memory (CAM) circuit according to claim 15 , and further comprising a polysilicon region forming a local interconnect between the compare circuit and first memory cell.

25. A content addressable memory (CAM) circuit according to claim 15 , and further comprising a polysilicon and conductive region forming a local interconnect between the compare circuit and the second memory cell.

26. A content addressable memory (CAM) circuit according to claim 15 , wherein said common terminal for first and second memory cells has a voltage potential of about one-half the voltage potential for the memory cells.