Semiconductor device with floating block
View Patent ↗A band gap circuit using NPN transistors ( 10, 12 ) having collectors connected to a power source voltage is employed, and transistor active regions of the NPN transistors ( 10, 12 ) and semiconductor elements constituting other signal processing circuits are integrated in the same floating block ( 19 ) with high voltage resistance. As a result, a reference voltage circuit used in the signal processing circuit can be integrated in a compact manner.
1. A semiconductor device comprising:
a high-potential power source terminal to be applied with a power source voltage varying from a low potential to a high potential;
a floating block configured as an island by surrounding a semiconductor layer formed on a semiconductor substrate with a separation-and-diffusion region, the potential of the island being biased by the voltage of said high-potential power source terminal;
a MOS transistor having a source connected to a low-potential power source terminal and outputting a reference voltage between said high-potential power source terminal and a drain;
first and second bipolar transistors having collectors and bases connected to said high-potential power source terminal;
a first resistor connected between the emitter of said first bipolar transistor and the drain of said MOS transistor;
second and third resistors connected in series between the emitter of said second bipolar transistor and the drain of said MOS transistor; and
a differential amplifier for controlling conduction of said MOS transistor by comparing an intermediate connection point of said second and third resistors and the emitter potential of said first bipolar transistor, wherein
the transistor active region of said first and second bipolar transistors, said MOS transistor, and said first to third resistors are formed within said floating block.
2. The semiconductor device according to claim 1 , wherein said floating block has a central portion thereof as an element formation region, guard rings are formed so as to surround the outer periphery of said element formation region.
3. The semiconductor device according to claim 1 , further comprising fourth and fifth resistors connected in series between said low-potential power source terminal and said high-potential power source terminal, and a comparator for comparing a drain potential of said MOS transistor and a potential at an intermediate connection point created by said fourth and fifth resistors, wherein an output signal of a signal processing circuit integrated in the element formation region within said floating block is terminated by an output of said comparator.
4. The semiconductor device according to claim 1 , further comprising a third bipolar transistor having a constant-current source connected to the emitter, and a collector and base connected to said high-potential power source terminal, and a second comparator for comparing a voltage between the base and emitter of said third bipolar transistor with a prescribed voltage based on the reference voltage, wherein an output signal of a signal processing circuit integrated in the element formation region within said floating block is terminated by an output of said second comparator.