Method and system for cache utilization by limiting prefetch requests
View Patent ↗System and method of memory utilization in a computer system are described. In one embodiment, the method comprises, responsive to receipt of a DMA transaction from an entity, determining whether a number of pending memory requests for the entity is less than a prefetch limit therefor; and responsive to a determination that the number of pending memory requests for the entity is less than the prefetch limit therefor, issuing a new memory request comprising a portion of the received DMA transaction.
1. A memory utilization method in a computer system, the method comprising:
for each entity of a plurality of entities connected to an input/output controller, calculating a corresponding prefetch limit based at least in part on a corresponding bandwidth available between the entity and the input/output controller;
responsive to receipt of a DMA transaction from an entity of the plurality of entities, determining whether a number of pending memory requests for the entity is less than the corresponding prefetch limit; and
responsive to a determination that the number of pending memory requests for the entity is less than the corresponding prefetch limit, issuing a new memory request comprising a portion of the received DMA transaction.
2. The method of claim 1 further comprising, responsive to a determination that the number of pending memory requests for the entity is not less than the corresponding prefetch limit, waiting until the number of pending memory requests for the entity falls below the corresponding prefetch limit to issue the new memory request.
3. The method of claim 1 further comprising, responsive to receipt of a DMA transaction from the entity, dividing the received DMA transaction into a number of cache line-sized memory requests.
4. The method of claim 1 wherein a value equal to a summation of corresponding prefetch limits for each of the plurality of entities is greater than the total number of cache lines in the cache and an additional request limit is applied before a new memory request is issued.
5. The method of claim 1 wherein the entity is an I/O card and the corresponding prefetch limit is equal to the corresponding bandwidth available times memory latency divided by a number of bytes in each cache line of a cache memory of the computer system.
6. The method of claim 5 wherein the cache memory is an input/output (“I/O”) cache memory.
7. The method of claim 5 wherein the cache memory is a coherent cache memory.
8. The method of claim 1 wherein the DMA transaction comprises a DMA read request.
9. The method of claim 1 wherein the corresponding prefetch limit is calculated at boot time or when a new entity is attached to the input/output controller.
10. A memory utilization method in a computer system, the method comprising:
for each entity of a plurality of entities connected to an input/output controller, calculating a corresponding prefetch limit based at least in part on an available bandwidth between the entity and the input/output controller;
responsive to receipt of a DMA transaction from an entity of the plurality of entities, dividing the DMA transaction into a number of cache line-sized memory requests and determining whether a number of pending memory requests for the entity is less than the corresponding prefetch limit; and
responsive to a determination that the number of pending memory requests for the entity is less than the corresponding prefetch limit, issuing a new memory request comprising a portion of the received DMA transaction.
11. The method of claim 10 further comprising, responsive to a determination that the number of pending memory requests for the entity is not less than the corresponding prefetch limit, waiting until the number of pending memory requests falls below the corresponding prefetch limit to issue the new memory request.
12. The method of claim 10 wherein a value equal to a summation of corresponding prefetch limits for each of the plurality of entities is greater than the total number of cache lines in the cache and an additional request limit is applied before a new memory request is issued.
13. The method of claim 12 wherein the entity is an I/O card and the corresponding prefetch limit is equal to the corresponding bandwidth available times memory latency divided by a number of bytes in each cache line of a cache memory of the computer system.
14. The method of claim 13 wherein the cache memory is en input/output (“I/O”) cache memory.
15. The method of claim 13 wherein the cache memory is a coherent cache memory.
16. The method of claim 10 wherein the corresponding prefetch limit is calculated at boot time or when a new entity is attached to the input/output controller.
17. The method of claim 10 wherein the DMA transaction comprises a DMA write request.
18. A system for performing DMA transactions in a computer, the system comprising:
means for calculating a corresponding prefetch limit for each entity of a plurality of entities connected to an input/output controller, the calculating based at least in part on a corresponding bandwidth available between the entity and the input/output controller;
cache means for storing data in connection with DMA transactions;
means responsive to receipt of a DMA transaction from an entity of the plurality of entities for determining whether a number of pending memory requests for the entity is less than a corresponding prefetch limit; and
means, responsive to a determination that the number of pending memory requests for the entity is less than the corresponding prefetch limit, for issuing a new memory request comprising a portion of the received DMA transaction.
19. The system of claim 18 further comprising means, responsive to a determination that the number of pending memory request for the entity is not less than the corresponding prefetch limit, for waiting until the number of pending memory requests for the entity falls below the corresponding prefetch limit to issue the new memory request.
20. The system of claim 19 wherein the cache means is a coherent cache memory.
21. The system of claim 18 further comprising means responsive to receipt of a DMA transaction from the entity for dividing the received DMA transaction into a number of cache line-sized memory requests.
22. The system of claim 18 wherein a value equal to a summation of corresponding prefetch limits for each of the plurality of entities is greater than the total number of cache lines in the cache means and further comprising means for applying an additional request limit before a new memory request is issued.
23. The system of claim 18 wherein the entity is an I/O card and the corresponding prefetch limit is equal to the corresponding bandwidth available times memory latency divided by a number of bytes in each cache line of the cache means.
24. The system of claim 18 wherein the cache means is an input/output (“I/O”) cache memory.
25. A computer-readable medium operable with a computer for performing DMA transactions in a computer, the medium having stored thereon:
instructions executable by the computer for calculating a corresponding prefetch limit for each entity of a plurality of entities connected to an input/output controller, the corresponding prefetch limit based at least in part on a corresponding bandwidth available between the entity and the input/output controller;
instructions executable by the computer responsive to receipt of a DMA transaction from an entity of the plurality of entities for determining whether a number of pending memory requests for the entity is less than a corresponding prefetch limit; and
instructions executable by the computer responsive to a determination that the number of pending memory requests for the entity is less than the corresponding prefetch limit, for issuing a new memory request comprising a portion of the received DMA transaction.
26. The medium of claim 25 further having stored thereon instructions executable by the computer responsive to a determination that the number of pending memory requests for the entity is not less than the corresponding prefetch limit therefor for waiting until the number of pending memory requests falls below the corresponding prefetch limit for the entity to issue the new memory request.
27. The medium of claim 26 further having stored thereon instructions executable by the computer responsive to the new memory request winning an arbitration for processing the new memory request.
28. The medium of claim 26 further having stored thereon instructions executable by the computer responsive to receipt of a DMA transaction from the entity for dividing the received DMA transaction into a number of cache line-sized memory requests.
29. The medium of claim 25 wherein the entity is an I/O card and the corresponding prefetch limit is equal to the corresponding bandwidth available times memory latency divided by a number of bytes in each cache line of a cache of the computer.