IP Library › Granted Patent US 7,863,128
Granted Patent B1
US 7,863,128 · App. 11/049,855 · Granted Jan 4, 2011

Non-volatile memory device with improved erase speed

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Quick Facts
Patent No.
US 7,863,128
App. No.
11/049,855
Filed
Feb 4, 2005
Granted
Jan 4, 2011
Kind
B1
Art Unit
2814
USPC
438/238
Abstract

A memory device may include a substrate, a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may also include a second dielectric layer formed over the charge storage element and a third dielectric layer formed over the second dielectric layer. The third dielectric layer may have a high dielectric constant and may be deposited at a relatively high temperature. A control gate may be formed over the third dielectric layer.

Claims (18)

1. A method of manufacturing a semiconductor device, comprising:

forming a first dielectric layer over a substrate;

forming a dielectric charge storage element directly on the first dielectric layer;

forming a second dielectric layer directly on the dielectric charge storage element;

depositing aluminum oxide at a temperature greater than 325° C. and directly on the second dielectric layer, where depositing the aluminum oxide includes depositing an aluminum oxide layer having a thickness ranging from about 30 Å to about 200 Å; and

forming a control gate over the aluminum oxide.

2. The method of claim 1 , where the dielectric charge storage element comprises a nitride.

3. The method of claim 1 , where depositing the aluminum oxide at a temperature greater than 325° C. comprises:

depositing aluminum oxide at a temperature ranging from greater than 400° C. to about 500° C.

4. The method of claim 1 , where depositing the aluminum oxide comprises:

depositing the aluminum oxide using an atomic layer deposition process.

5. The method of claim 1 , where forming the dielectric charge storage element comprises:

forming a nitride layer having a thickness ranging from about 20 Å to about 100 Å.

6. The method of claim 5 , where forming the second dielectric layer comprises:

Forming a silicon oxide layer having a thickness ranging from about 15 Å to 100 Å.

7. The method of claim 1 , where depositing the aluminum oxide further includes depositing hafnium.

8. The method of claim 1 , further comprising:

forming a plurality of memory cells in the semiconductor device, where each of the memory cells stores charges representing two bits of information.