Ultrathin SOI transistor and method of making the same

1. A method of fabricating an ultrathin SOI memory transistor, comprising:

preparing a substrate, including forming an ultrathin SOI layer of the substrate;

adjusting the threshold voltage of the SOI layer;

depositing a layer of silicon oxide on the SOI layer;

patterning and etching the silicon oxide layer to form a sacrificial oxide gate in a gate region;

depositing a layer of silicon nitride and forming the silicon nitride into a silicon nitride sidewall for the sacrificial oxide gate;

depositing a first layer of amorphous silicon;

smoothing the first layer of amorphous silicon by CMP;

selectively etching the sacrificial gate oxide;

growing a layer of oxide in the gate region;

depositing a second layer of amorphous silicon;

smoothing the second layer of amorphous silicon by CMP;

patterning and etching the first layer of amorphous silicon;

implanting ions to form a source region and a drain region;

annealing the structure to diffuse the implanted ions;

depositing a layer of passivation oxide;

patterning and etching the passivation oxide to form contact holes; and

metallizing the structure to complete the memory transistor.

2. The method of claim 1 which further includes, after said patterning and etching the first layer of amorphous silicon, depositing a refractory metal on the first layer of amorphous silicon and the second layer of amorphous silicon, and performing a salicide process.

3. The method of claim 1 wherein said forming an ultrathin SOI layer on the substrate includes forming a top silicon layer having a thickness of between about 10 nm to 20 nm.

4. The method of claim 1 wherein said depositing a layer of silicon nitride includes depositing a layer of silicon nitride having a thickness of between about 10 nm to 50 nm.

5. The method of claim 1 wherein said depositing a first layer of amorphous silicon and said depositing a second layer of amorphous silicon includes depositing amorphous silicon to a thickness of between about 200 nm to 700 nm.

6. A method of fabricating an ultrathin SOI memory transistor, comprising:

preparing a substrate, including forming an ultrathin SOI layer of the substrate;

adjusting the threshold voltage of the SOI layer;

depositing a layer of silicon oxide on the SOI layer;

patterning and etching the silicon oxide layer to form a sacrificial oxide gate in a gate region;

depositing a layer of silicon nitride and forming the silicon nitride into a silicon nitride sidewall for the sacrificial oxide gate;

depositing a first layer of amorphous silicon;

smoothing the layer of amorphous silicon by CMP;

selectively etching the sacrificial gate oxide;

growing a layer of oxide in the gate region;

depositing a second layer of amorphous silicon;

smoothing the second layer of amorphous silicon by CMP;

depositing a refractory metal on the second layer of amorphous silicon and performing a salicide process;

patterning and etching the first layer of amorphous silicon;

implanting ions to form a source region and a drain region;

annealing the structure to diffuse the implanted ions;

depositing a layer of passivation oxide;

patterning and etching the passivation oxide to form contact holes; and

metallizing the structure to complete the memory transistor.

7. The method of claim 6 wherein said forming an ultrathin SOI layer on the substrate includes forming a top silicon layer having a thickness of between about 10 nm to 20 nm.

8. The method of claim 6 wherein said depositing a layer of silicon nitride includes depositing a layer of silicon nitride having a thickness of between about 10 nm to 50 nm.

9. The method of claim 6 wherein said depositing a first layer of amorphous silicon and said depositing a second layer of amorphous silicon includes depositing amorphous silicon to a thickness of between about 200 nm to 700 nm.