5 volt tolerant IO scheme using low-voltage devices
View Patent ↗Systems and methods are disclosed for operating a core circuitry of an integrated circuit at a lower voltage than the coupled IO circuitry using a tolerant circuit. In one embodiment includes a voltage tolerant circuit comprising a voltage detect module adapted to detect when a voltage is sufficient to switch bias conditions without violating maximum transistor operating conditions and a comparator adapted to detect when a PAD voltage is greater than an IO power supply voltage.
1. A method of operating an integrated circuit using a voltage tolerant circuit comprising:
a step of detecting when a voltage is sufficient to switch bias conditions without violating maximum transistor operating conditions;
a step of detecting when a PAD voltage is greater than an IO power supply voltage; and
decoupling said PAD voltage when said PAD voltage is less than a voltage of a core power supply plus a threshold voltage of a voltage detect module.
2. The method of claim 1 comprising a step of switching between an intermediate power voltage and an IO power voltage.
3. The method of claim 1 comprising a step of ensuring that a PMOS transistor device will not turn on when said PAD voltage exceeds said IO power supply voltage.
4. The method of claim 1 comprising a step of preventing at least one transistor device from being overstressed.
5. The method of claim 1 comprising a step of preventing overstress when a voltage of a floating well is greater than said PAD voltage.
6. The method of claim 1 comprising a step of preventing overstress when a voltage of a floating well is greater than said IO power supply voltage.
7. A method of operating an integrated circuit using a voltage tolerant circuit comprising:
a step of detecting when a voltage is sufficient to switch bias conditions without violating maximum transistor operating conditions using a voltage detect module of the voltage tolerant circuit;
a step of detecting when a PAD voltage is greater than an IO power supply voltage using a comparator of said voltage detect module; and
a step of switching between an intermediate power voltage and an IO power supply voltage using a switching transistor device.
8. The method of claim 7 , wherein said comparator comprises at least one device.
9. The method of claim 7 , wherein said comparator comprises two PMOS transistor device.
10. The method of claim 7 comprising a step of ensuring that a PMOS transistor device will not turn on when said PAD voltage exceeds said IO power supply voltage using a tri-state module.
11. The method of claim 10 , wherein said tri-state module comprises at least one device.
12. The method of claim 10 , wherein said tri-state module comprises at least one PMOS transistor device.
13. The method of claim 10 , wherein said tri-state module comprises at least one NMOS transistor device.
14. The method of claim 7 comprising a step of preventing at least one transistor device from being overstressed using an overstress module.
15. The method of claim 14 , wherein said overstressed module comprises at least one device.
16. The method of claim 14 , wherein said overstressed module comprises three NMOS transistor devices.
17. The method of claim 14 comprising a step of preventing said overstress when a voltage of a floating well is greater than said PAD voltage using said overstress module.
18. The method of claim 14 comprising a step of preventing said overstress when a voltage of a floating well is greater than said IO power supply voltage using said overstress module.
19. The method of claim 7 comprising a step of switching between an intermediate power voltage and an IO power voltage using a switching transistor.
20. The method of claim 7 comprising decoupling said PAD Voltage from at least one device in said comparator when said PAD voltage is less than a predetermined voltage using a transistor device.
21. The method of claim 20 wherein said predetermined voltage comprises a voltage of a core power supply plus a threshold voltage of said voltage detect module.