IP Library Granted Patent US 7,987,333
Granted Patent B2
US 7,987,333 · App. 11/051,300 · Granted Jul 26, 2011

Reprogramming of select registers in a linked list

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Quick Facts
Patent No.
US 7,987,333
App. No.
11/051,300
Granted
Jul 26, 2011
Kind
B2
Abstract

A system and method, for reprogramming registers without having to reprogram unchanged registers. The registers are divided into groups based on common characteristics or functions. The values for the groups that differ from the current values are written into a linked list, which is then loaded into the appropriate registers. The linked list contains information indicating the groups of registers in the linked list.

Claims (29)

1. A method for decoding video data, said method comprising:

determining some of a plurality of groups of registers are to be reprogrammed during one point during the display period of a frame and a remainder of the groups of registers are not to be reprogrammed at any point during the display period of the frame; and

writing a linked list containing the values for each of the some of the plurality of groups of registers that are to be reprogrammed, wherein the values for the some of the plurality of groups of registers are continuous in said linked list;

wherein during the display period of the frame, both even lines and odd lines are displayed;

writing an indicator for each of the plurality of groups of registers, indicating whether each of the groups of registers are to be reprogrammed in a predetermined order; and

wherein the linked list is in an order related to the predetermined order.

2. The method of claim 1 , wherein the values in the linked list comprise varying amounts of data.

3. The method of claim 1 , further comprising:

allocating an amount of memory for the linked list;

determining another some of a plurality of groups of registers that are to be reprogrammed and another remainder of the groups of registers are not to be reprogrammed;

allocating another amount of memory; and

writing another linked list containing the values for each of the some of the plurality of groups of registers that are to be reprogrammed in the memory, wherein the values for the some of the plurality of groups of registers are continuous in said linked list.

4. A system for decoding video data, said system comprising:

a plurality of groups of registers;

a host processor;

a data memory; and

a program memory for storing a plurality of instructions, wherein execution of the plurality of instructions by the processor causes:

determining some of a plurality of groups of registers are to be reprogrammed during one point during the display period of a frame and a remainder of the groups of registers are not to be reprogrammed at any point during the display period of frame; and

writing a linked list containing the values for each of the some of the plurality of groups of registers that are to be reprogrammed, wherein the values for the some of the plurality of groups of registers are continuous in said linked list to the data memory; and

wherein the host processor is configured to execute the plurality of instructions after receiving a vertical synchronization pulse;

wherein during the display period of the frame, both even lines and odd lines are displayed;

writing an indicator for each of the plurality of groups of registers, indicating whether each of the groups of registers are to be reprogrammed in a predetermined order to the data memory; and

wherein the linked list is in an order related to the predetermined order.

5. The system of claim 4 , wherein the values in the linked list comprise varying amounts of data.

6. The system of claim 4 , further comprising:

allocating an amount of data memory for the linked list;

determining another some of a plurality of groups of registers that are to be reprogrammed and another remainder of the groups of registers are not to be reprogrammed;

allocating another amount of data memory; and

writing another linked list containing the values for each of the some of the plurality of groups of registers that are to be reprogrammed in the data memory, wherein the values for the some of the plurality of groups of registers are continuous in said linked list.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE PROPERTY NUMBERS PREVIOUSLY RECORDED AT REEL: 47630 FRAME: 344. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 21, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0267 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 9/5/2018 PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0687. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0344 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0687 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 6, 2005
From: SANE, ANIRUDDHA; CHATEKAR, NAGESH; TANG, CHENGFUH JEFFREY; NISSEN, GLENN
To: BROADCOM CORPORATION
Reel/Frame 016015/0455 →