Array substrate for liquid crystal display device and method of manufacturing the same
View Patent ↗An array substrate for a liquid crystal display device includes a plurality of gate lines formed of a first material and a plurality of data lines formed of a second material on a substrate, the plurality of gate lines and the plurality of data lines crossing each other, a plurality of thin film transistors electrically connected to the plurality of gate lines and the plurality of data lines, a plurality of pixel electrodes connected to the plurality of thin film transistors, a plurality of gate pads connected to the plurality of gate lines, a plurality of data pads connected to the plurality of data lines, a first shorting bar electrically connected to odd-numbered gate pads, the first shorting bar made of the first material, a second shorting bar electrically connected to even-numbered gate pads, the second shorting bar made of the second material, a third shorting bar electrically connected to odd-numbered data pads, the third shorting bar made of the first material, a fourth shorting bar electrically connected to even-numbered data pads, the fourth shorting bar made of the second material, first, second, third, and fourth connection lines electrically connected to the first, second, third, and fourth shorting bars, respectively, the first, second, third, and fourth connection lines made of the first material, and first, second, third, and fourth test pads connected to the first, second, third, and fourth connection lines, respectively, the first, second, third, and fourth test pads made of the first material.
1. An array substrate for a liquid crystal display device, comprising:
a substrate;
a plurality of gate lines and a plurality of data lines crossing each other on the substrate;
plurality of thin film transistors electrically connected to the plurality of gate lines and the plurality of data lines;
a plurality of pixel electrodes connected to the plurality of thin film transistors;
a plurality of odd-numbered and even-numbered gate pads connected to the plurality of gate lines;
a plurality of odd-numbered and even-numbered data pads connected to the plurality of data lines;
a first shorting bar electrically connected to each of the odd-numbered gate pads, the first shorting bar made of a first material;
a second shorting bar electrically connected to each of the even-numbered gate pads, the second shorting bar made of a second material different from the first material;
a third shorting bar electrically connected to each of the odd-numbered data pads, the third shorting bar made of the first material;
a fourth shorting bar electrically connected to each of the even-numbered data pads, the fourth shorting bar made of the second material;
first, second, third, and fourth connection lines electrically connected to the first, second, third, and fourth shorting bars, respectively, the first, second, third, and fourth connection lines made of the first material; and
first, second, third, and fourth test pads connected to the first, second, third, and fourth connection lines, respectively, the first, second, third, and fourth test pads made of the first material.
2. The array substrate according to claim 1 , further comprising a first conducting pattern electrically connecting the second shorting bar to the second connection line, and a second conducting pattern electrically connecting the fourth shorting bar to the fourth connection line.
3. The array substrate according to claim 1 , wherein the second material includes molybdenum.
4. The array substrate according to claim 1 , wherein the first material includes a first layer and a second layer.
5. The array substrate according to claim 4 , wherein the first layer includes aluminum, and the second layer includes some of the chromium and molybdenum.
6. The array substrate according to claim 1 , wherein each of the plurality of thin film transistors includes a gate electrode, a source electrode, a data electrode, and an active layer, the active layer having the same shape as the source electrode and the drain electrode except for a portion between the source and drain electrodes.
7. The array substrate according to claim 1 , wherein the plurality of gate lines are formed of the first material.
8. The array substrate according to claim 1 , wherein the plurality of data lines are formed of the second material.