System and method for block write to memory
View Patent ↗A hardware implemented method for writing data to a cache is provided. In this hardware implemented method, a Block Initializing Store (BIS) instruction is received to write the data from a processor core to a memory block. The BIS instruction includes the data from the processor core. Thereafter, a dummy read request is sent to a memory controller and known data is received from the memory controller without accessing a main memory. The known data is then written to the cache and, after the known data is written, the data from the processor core is written to the cache. A system and processor for writing data to the cache also are described.
1. A hardware implemented method for writing data to a cache, comprising method operations of:
receiving a Block Initializing Store (BIS) instruction to write the data from a processor core to a memory block, the BIS instruction including the data from the processor core;
determining whether the BIS instruction is to address zero of a cache line;
if the BIS instruction is to the address zero, sending a dummy read request to a memory controller;
receiving known data from the memory controller without accessing a main memory;
writing the known data to the cache; and
writing the data from the processor core to the cache after writing the known data.
2. The hardware implemented method of claim 1 , wherein the dummy read request is a request that does not require an actual read from the main memory.
3. The hardware implemented method of claim 1 , wherein the BIS instruction is received from the processor core and the BIS instruction misses the cache.
4. The hardware implemented method of claim 1 , further comprising:
if a data path between the processor core and the cache is smaller than size of the data, receiving a plurality of the BIS instructions to write portions of the data to the memory block.
5. The hardware implemented method of claim 1 , wherein the method operation of writing the known data to the cache includes,
writing zeros to the cache without accessing the main memory.
6. The hardware implemented method of claim 1 , further comprising:
sending a read request to the memory controller, the read request enabling the memory controller to access the main memory.
7. The hardware implemented method of claim 1 , wherein the method operation of writing the known data to the cache includes,
writing the known data to the cache at a memory address indicated by the BIS instruction.
8. A processor having circuitry for writing data to a cache, comprising:
circuitry for receiving an instruction to write the data from a processor core to a memory block, the instruction including the data from the processor core;
circuitry for determining whether the instruction is a Block Initializing Store (BIS) instruction;
circuitry for determining whether the BIS instruction is to address zero of a cache line; and
circuitry for sending a dummy read request to a memory controller if the BIS instruction is to the address zero.
9. The processor of claim 8 , further comprising:
circuitry for receiving known data from the memory controller;
circuitry for writing the known data to the cache; and
circuitry for writing the data from the processor core to the cache after writing the known data.
10. The processor of claim 9 , wherein the known data is defined by one of a zero, a one, or a data pattern.
11. The processor of claim 8 , wherein the memory controller includes,
circuitry for receiving the dummy read request; and
circuitry for sending known data to the cache forgoing access to a main memory in response to the received dummy read request.
12. The processor of claim 8 , further comprising:
circuitry for receiving a plurality of the BIS instructions to write portions of the data to the memory block if a data path between the processor core and the cache is smaller than size of the data.