L2 cache array topology for large cache with different latency domains
View Patent ↗A cache memory logically associates a cache line with at least two cache sectors of a cache array wherein different sectors have different output latencies and, for a load hit, selectively enables the cache sectors based on their latency to output the cache line over successive clock cycles. Larger wires having a higher transmission speed are preferably used to output the cache line corresponding to the requested memory block. In the illustrative embodiment the cache is arranged with rows and columns of the cache sectors, and a given cache line is spread across sectors in different columns, with at least one portion of the given cache line being located in a first column having a first latency, and another portion of the given cache line being located in a second column having a second latency greater than the first latency. One set of wires oriented along a horizontal direction may be used to output the cache line, while another set of wires oriented along a vertical direction may be used for maintenance of the cache sectors. A given cache line is further preferably spread across sectors in different rows or cache ways. For example, a cache line can be 128 bytes and spread across four sectors in four different columns, each sector containing 32 bytes of the cache line, and the cache line is output over four successive clock cycles with one sector being transmitted during each of the four cycles.
1. A cache memory comprising: an output;
a cache array having a plurality of cache lines, different portions of each cache line being stored in a respective plurality of cache sectors having different latencies to said output;
a cache directory which determines that a given cache line contains a current, valid copy of a requested memory block; and
a cache controller that selectively enables cache sectors of the given cache line based on their latencies to transmit the portions of the given cache line to said output over successive clock cycles.
2. The cache memory of claim 1 wherein smaller wires having a lower transmission speed are used to input data into said cache array, and larger wires having a higher transmission speed are used to output the cache line corresponding to the requested memory block.
3. The cache memory of claim 1 wherein said cache controller schedules different tasks for different cache sectors to be carried out simultaneously.
4. The cache memory of claim 1 wherein said cache array is arranged with rows and columns of said cache sectors, and a given cache line is spread across sectors in different columns, with at least one portion of the given cache line being located in a first column having a first latency, and another portion of the given cache line being located in a second column having a second latency greater than the first latency.
5. The cache memory of claim 4 wherein a first set of wires oriented along a horizontal direction are used to output the cache line, and a second set of wires oriented along a vertical direction are used for maintenance of said cache sectors.
6. The cache memory of claim 4 wherein a given cache line is further spread across sectors in different rows.
7. The cache memory of claim 4 wherein:
a cache line is 128 bytes and spread across four sectors in four different columns, each sector containing 32 bytes of the cache line; and
the cache line is output over four successive clock cycles with one sector being transmitted during each of the four cycles.
8. A computer system comprising:
one or more processors which process program instructions;
a memory device; and
a cache memory connected to said one or more processors and said memory device to temporarily store values that are used by said one or more processors, said cache memory including an output,
a cache array having a plurality of cache lines, different portions of each cache line being stored in a respective plurality of cache sectors having different latencies to said output,
a cache directory which determines that a given cache line contains a current, valid copy of a memory block requested by said one or more processors, and
a cache controller that selectively enables cache sectors associated with the given cache line based on their latencies to transmit the portions of the given cache line to said output over successive clock cycles.
9. The computer system of claim 8 wherein smaller wires having a lower transmission speed are used to input data into said cache array, and larger wires having a higher transmission speed are used to output the cache line corresponding to the requested memory block to said one or more processors.
10. The computer system of claim 8 wherein said cache controller schedules different tasks for different cache sectors to be carried out simultaneously.
11. The computer system of claim 8 wherein said cache array is arranged with rows and columns of said cache sectors, and a given cache line is spread across sectors in different columns, with at least one portion of the given cache line being located in a first column having a first latency, and another portion of the given cache line being located in a second column having a second latency greater than the first latency.
12. The computer system of claim 11 wherein a first set of wires oriented along a horizontal direction are used to output the cache line, and a second set of wires oriented along a vertical direction are used for maintenance of said cache sectors.
13. The computer system of claim 11 wherein a given cache line is further spread across sectors in different rows.