Ramp generators for imager analog-to-digital converters
View Patent ↗An imager with an analog-to-digital converter having at least one ramp generator that precisely and efficiently produces the desired ramp voltages required by the analog-to-digital converter. The analog-to-digital converter can use differential or two ramp generators. The analog-to-digital converter can also use ramp generators operated in linear or compressed ramp modes.
1. An analog-to-digital converter comprising:
a ramp generator having a differential ramp voltage output;
a comparison circuit connected to receive the differential ramp voltage output, said comparison circuit inputting first and second analog signals and generating a comparison signal when the input signals match the differential ramp voltage output; and
a latching circuit coupled to the comparison signal, said latching circuit latching a digital code corresponding to a difference between the input first and second analog signals when the comparison signal indicates that the input signals match the differential ramp voltage output.
2. The analog-to-digital converter of claim 1 wherein said ramp generator comprises first and second ramp generator circuits, said first ramp generator circuit having a first ramp output and said second ramp generator having a second ramp output.
3. The analog-to-digital converter of claim 2 , wherein the first ramp output is a falling ramp voltage and the second ramp output is a rising ramp voltage.
4. The analog-to-digital converter of claim 2 , wherein the first ramp output is compared to the first analog signal and the second ramp output is compared to the second analog signal.
5. The analog-to-digital converter of claim 1 , wherein said ramp generator comprises:
a plurality of ramp unit cells having respective voltage outputs; and
a shift register connected to the ramp unit cells, said shift register controlling an operation of the unit cells,
wherein a combined voltage output of the ramp unit cells is used as a ramp voltage output for said ramp generator circuit.
6. The analog-to-digital converter of claim 1 , wherein said ramp generator comprises a plurality of ramp unit cells and each ramp unit cell comprises:
a rising voltage portion having a rising voltage output;
a falling voltage portion having a falling voltage output; and
a shift register having an output that controls said rising and falling voltage portions,
wherein the rising voltages of each ramp unit cell are combined to form a combined rising voltage output and the falling voltages of each ramp unit cell are combined to form a combined falling voltage output, the combined voltage outputs forming the differential ramp voltage output.
7. The analog-to-digital converter of claim 6 , wherein said rising voltage portion comprises:
an inverter connected to the shift register output;
a pair of serially connected transistors connected between a low potential and a reference potential and being controlled by the inverter output;
a clamping circuit;
a reset circuit connected to the clamping circuit; and
a capacitor connected between the serially connected pair and a connection of the clamping and reset circuits, wherein charge stored on the capacitor is used as the rising voltage output.
8. The analog-to-digital converter of claim 7 , wherein the pair of serially connected transistors comprises a p-channel transistor used to pull the rising voltage output to the reference potential at an end of a ramp operation.
9. The analog-to-digital converter of claim 6 , wherein said falling voltage portion comprises:
an inverter connected to the shift register output;
a pair of serially connected transistors connected between a high potential and a reference potential and being controlled by the inverter output;
a clamping circuit;
a reset circuit connected to the clamping circuit; and
a capacitor connected between the serially connected pair and a connection of the clamping and reset circuits, wherein charge stored on the capacitor is used as the falling voltage output.
10. The analog-to-digital converter of claim 9 , wherein the pair of serially connected transistors comprises an n-channel transistor used to pull the falling voltage output to the reference potential at an end of a ramp operation.
11. The analog-to-digital converter of claim 1 , wherein the ramp voltage output is linear.
12. The analog-to-digital converter of claim 1 , wherein the ramp voltage output is non-linear.
13. The analog-to-digital converter of claim 1 , wherein said ramp generator is a multi-mode ramp generator.
14. The analog-to-digital converter of claim 13 , wherein said ramp generator comprises a plurality of ramp unit cells, said cells being organized into a plurality of rows, wherein half of said rows are arranged in a first direction and half of said rows are arranged in a second direction.
15. The analog-to-digital converter of claim 14 , wherein an output of a row arranged in the first direction is used as an input for a row arranged in the second direction.
16. The analog-to-digital converter of claim 14 , wherein an output of a row arranged in the second direction is used as an input for a row arranged in the first direction.
17. The analog-to-digital converter of claim 14 , wherein a combined voltage output of the rows is used as the ramp voltage output.
18. The analog-to-digital converter of claim 17 , wherein the rows are connected such that the ramp voltage output is linear.
19. The analog-to-digital converter of claim 17 , wherein the rows are connected such that the ramp voltage output is compressed.
20. The analog-to-digital converter of claim 13 , wherein said ramp generator has multiple compressed operating modes, each compressed operating mode having a programmable break point.
21. The analog-to-digital converter of claim 20 , wherein said ramp generator comprises a plurality of current sources and said break points are programmed by switching in current sources.
22. An analog-to-digital converter comprising:
a multimode ramp generator having a multimode ramp voltage output;
a comparison circuit connected to receive the multimode ramp voltage output, said comparison circuit inputting an analog signal and generating a comparison signal when the input signal matches the multimode ramp voltage output; and
a latching circuit coupled to the comparison signal, said latching circuit latching a digital code corresponding to the input analog signal.
23. The analog-to-digital converter of claim 22 , wherein the ramp voltage output is linear.
24. The analog-to-digital converter of claim 22 , wherein the ramp voltage output is non-linear.
25. The analog-to-digital converter of claim 22 , wherein said ramp generator comprises a plurality of ramp unit cells, said cells being organized into a plurality of rows, wherein half of said rows are arranged in a first direction and half of said rows are arranged in a second direction.
26. The analog-to-digital converter of claim 25 , wherein an output of a row arranged in the first direction is used as an input for a row arranged in the second direction.
27. The analog-to-digital converter of claim 25 , wherein an output of a row arranged in the second direction is used as an input for a row arranged in the first direction.
28. The analog-to-digital converter of claim 25 , wherein a combined voltage output of the rows is used as the ramp voltage output.
29. The analog-to-digital converter of claim 28 , wherein the rows are connected such that the ramp voltage output is linear.
30. The analog-to-digital converter of claim 28 , wherein the rows are connected such that the ramp voltage output is compressed.
31. The analog-to-digital converter of claim 22 , wherein said ramp generator has multiple compressed operating modes, each compressed operating mode having a programmable break point.
32. The analog-to-digital converter of claim 31 , wherein said ramp generator comprises a plurality of current sources and said break points are programmed by switching in current sources.
33. An imaging device comprising:
an array of pixels, said array outputting analog signals; and
an analog-to-digital converter coupled to the array, said analog-to-digital converter comprising:
a ramp generator having a differential ramp voltage output,
a comparison circuit connected to receive the differential ramp voltage output, said comparison circuit inputting first and second analog signals and generating a comparison signal when the input signals match the differential ramp voltage output, and
a latching circuit coupled to the comparison signal, said latching circuit latching a digital code corresponding to a difference between the input first and second analog signals when the comparison signal indicates that the input signals match the differential ramp voltage output.
34. The device of claim 33 , wherein said ramp generator comprises first and second ramp generator circuits, said first ramp generator circuit having a first ramp output and said second ramp generator having a second ramp output.
35. The device of claim 34 , wherein the first ramp output is a falling ramp voltage and the second ramp output is a rising ramp voltage.
36. The device of claim 35 , wherein the first ramp output is compared to the first analog signal and the second ramp output is compared to the second analog signal.
37. The device of claim 33 , wherein said ramp generator comprises:
a plurality of ramp unit cells having respective voltage outputs; and
a shift register connected to the ramp unit cells, said shift register controlling an operation of the unit cells,
wherein a combined voltage output of the ramp unit cells is used as a ramp voltage output for said ramp generator circuit.
38. The device of claim 33 , wherein said ramp generator comprises a plurality of ramp unit cells and each ramp unit cell comprises:
a rising voltage portion having a rising voltage output;
a falling voltage portion having a falling voltage output; and
a shift register having an output that controls said rising and falling voltage portions,
wherein the rising voltages of each ramp unit cell are combined to form a combined rising voltage output and the falling voltages of each ramp unit cell are combined to form a combined falling voltage output, the combined voltage outputs forming the differential ramp voltage output.
39. The device of claim 38 , wherein said rising voltage portion comprises:
an inverter connected to the shift register output;
a pair of serially connected transistors connected between a low potential and a reference potential and being controlled by the inverter output;
a clamping circuit;
a reset circuit connected to the clamping circuit; and
a capacitor connected between the serially connected pair and a connection of the clamping and reset circuits, wherein charge stored on the capacitor is used as the rising voltage output.
40. The device of claim 39 , wherein the pair of serially connected transistors comprises a p-channel transistor used to pull the rising voltage output to the reference potential at an end of a ramp operation.
41. The device of claim 39 , wherein said falling voltage portion comprises:
an inverter connected to the shift register output;
a pair of serially connected transistors connected between a high potential and a reference potential and being controlled by the inverter output;
a clamping circuit;
a reset circuit connected to the clamping circuit; and
a capacitor connected between the serially connected pair and a connection of the clamping and reset circuits, wherein charge stored on the capacitor is used as the falling voltage output.
42. The device of claim 41 , wherein the pair of serially connected transistors comprises an n-channel transistor used to pull the falling voltage output to the reference potential at an end of a ramp operation.
43. The device of claim 33 , wherein the ramp voltage output is linear.
44. The device of claim 33 , wherein the ramp voltage output is non-linear.
45. The device of claim 33 , wherein said ramp generator is a multi-mode ramp generator.
46. The device of claim 45 , wherein said ramp generator comprises a plurality of ramp unit cells, said cells being organized into a plurality of rows, wherein half of said rows are arranged in a first direction and half of said rows are arranged in a second direction.
47. The device of claim 46 , wherein an output of a row arranged in the first direction is used as an input for a row arranged in the second direction.
48. The device of claim 46 , wherein an output of a row arranged in the second direction is used as an input for a row arranged in the first direction.
49. The device of claim 46 , wherein a combined voltage output of the rows is used as the ramp voltage output.
50. The device of claim 49 , wherein the rows are connected such that the ramp voltage output is linear.
51. The device of claim 49 , wherein the rows are connected such that the ramp voltage output is compressed.
52. The device of claim 45 , wherein said ramp generator has multiple compressed operating modes, each compressed operating mode having a programmable break point.
53. The device of claim 52 , wherein said ramp generator comprises a plurality of current sources and said break points are programmed by switching in current sources.
54. An imaging device comprising:
an array of pixels, said array outputting analog signals; and
an analog-to-digital converter coupled to the array, said analog-to-digital converter comprising:
a multimode ramp generator having a multimode ramp voltage output,
a comparison circuit connected to receive the multimode ramp voltage output, said comparison circuit inputting an analog signal and generating a comparison signal when the input signal matches the multimode ramp voltage output, and
a latching circuit coupled to the comparison signal, said latching circuit latching a digital code corresponding to the input analog signal.
55. The device of claim 54 , wherein the ramp voltage output is linear.
56. The device of claim 54 , wherein the ramp voltage output is non-linear.
57. The device of claim 54 , wherein said ramp generator comprises a plurality of ramp unit cells, said cells being organized into a plurality of rows, wherein half of said rows are arranged in a first direction and half of said rows are arranged in a second direction.
58. The device of claim 57 , wherein an output of a row arranged in the first direction is used as an input for a row arranged in the second direction.
59. The device of claim 57 , wherein an output of a row arranged in the second direction is used as an input for a row arranged in the first direction.
60. The device of claim 57 , wherein a combined voltage output of the rows is used as the ramp voltage output.
61. The device of claim 60 , wherein the rows are connected such that the ramp voltage output is linear.
62. The device of claim 60 , wherein the rows are connected such that the ramp voltage output is compressed.
63. The device of claim 54 , wherein said ramp generator has multiple compressed operating modes, each compressed operating mode having a programmable break point.
64. The device of claim 63 , wherein said ramp generator comprises a plurality of current sources and said break points are programmed by switching in current sources.
65. A processor system comprising:
a processor; and
an imaging device coupled to said process and comprising an array of pixels and an analog-to-digital converter coupled to said array, said array outputting analog signals, said analog-to-digital converter comprising:
a ramp generator having a differential ramp voltage output,
a comparison circuit connected to receive the differential ramp voltage output, said comparison circuit inputting first and second analog signals and generating a comparison signal when the input signals match the differential ramp voltage output, and
a latching circuit coupled to the comparison signal, said latching circuit latching a digital code corresponding to a difference between the input first and second analog signals when the comparison signal indicates that the input signals match the differential ramp voltage output.
66. A processor system comprising:
a processor; and
an imaging device coupled to said processor and comprising an array of pixels and an analog-to-digital converter coupled to said array, said array outputting analog signals, said analog-to-digital converter comprising:
a multimode ramp generator having a multimode ramp voltage output,
a comparison circuit connected to receive the multimode ramp voltage output, said comparison circuit inputting an analog signal and generating a comparison signal when the input signal matches the multimode ramp voltage output, and
a latching circuit coupled to the comparison signal, said latching circuit latching a digital code corresponding to the input analog signal.
67. A method of operating a ramp generator to be used with an analog-to-digital converter, said method comprising:
organizing a plurality ramp unit cells into a first configuration based on a first operating mode; and
combing the outputs of the ramp unit cells to form a ramp voltage output,
wherein the ramp generator has multiple compressed operating modes, each compressed operating mode has a programmable break point.
68. The method of claim 67 , wherein the organizing act comprises switchingly connecting a predetermined number of ramp unit cells based on the first operating mode.
69. The method of claim 67 , wherein the ramp generator comprises a plurality of current sources and said break points are programmed by switching in current sources.
70. A method of operating a ramp generator to be used with an analog-to-digital converter, said method comprising:
organizing a plurality ramp unit cells into a first configuration based on a first operating mode; and
combing the outputs of the ramp unit cells to form a ramp voltage output,
wherein the cells are organized into a plurality of rows, half of said rows are arranged in a first direction and half of said rows are arranged in a second direction.
71. The method of claim 70 , wherein an output of a row arranged in the first direction is used as an input for a row arranged in the second direction.
72. The method of claim 70 , wherein an output of a row arranged in the second direction is used as an input for a row arranged in the first direction.
73. The method of claim 70 , wherein the rows are connected such that the ramp voltage output is linear.
74. The device of claim 70 , wherein the rows are connected such that the ramp voltage output is compressed.