Method of testing apparatus having master logic unit and slave logic unit
View Patent ↗An apparatus which is tested includes a master logic unit and a slave logic unit. The testing method includes accessing a virtual slave logic unit by a test pattern which includes an address for accessing and an expected value of a waiting time, returning a response value from the virtual slave logic unit which is accessed by the address after lapse of the waiting time, and comparing the expected value and the response value.
1. A method of testing an apparatus which includes a master logic unit and a slave logic unit, comprising:
sending a test pattern which includes an expected value and a waiting time to a virtual slave logic unit and a transfer checker;
returning a response value from the virtual slave logic unit after a lapse of the waiting time;
comparing the expected value and the response value from the virtual slave logic unit; and
accessing the slave logic unit by the test pattern after the response value is returned by the virtual slave logic unit.
2. The method of claim 1 , wherein the master logic unit and the slave logic unit are connected by a bus, and wherein a virtual master logic unit sends the test pattern to the bus.
3. The method of claim 1 , wherein the virtual slave logic unit detects a number of clock cycles which correspond to the waiting time in the test pattern.
4. The method of claim 1 , further comprising a default slave logic unit which returns a response when the slave logic unit does not return any response, wherein the default slave logic unit is used as the virtual logic unit.