Interface apparatus and method for data recovery and synchronization

1. An interface apparatus for coupling a signal output to a signal input, comprising:

an analog/digital converter unit having an input for receiving an analog signal with a first component and a second component, and having an output for outputting a discrete-value signal associated with the analog signal, the discrete-value signal having a first component and a second component, wherein the analog signal represents a data symbol based on a coding;

a signal processor unit connected to the output of the analog/digital converter unit, and configured to output the data symbol represented by the analog signal to an output of the signal processor unit, wherein the signal processor unit comprises a signal processor configured to detect a frequency change or a change in a direction of rotation of the phase angle of the discrete-value signal applied to an input thereof; and

a delay unit connected to the output of the signal processor unit, wherein the delay unit comprises a memory unit configured to store at least two data symbols and further configured to provide the data symbol at an output thereof after an adjustable delay time.

2. The interface apparatus of claim 1 , wherein the memory unit comprises a plurality of memory cells for storing the at least two data symbols.

3. The interface apparatus of claim 1 , wherein the memory unit comprises a plurality of shift register cells.

4. The interface apparatus of claim 1 , wherein the delay unit further comprises a flipflop circuit at a data input of the delay unit, wherein an output of the flipflop circuit is coupled to the memory unit.

5. The interface apparatus of claim 1 , wherein a maximum delay time in providing the data symbol at the output of the delay unit is derived from a size of the memory in the memory unit.

6. The interface apparatus of claim 1 , wherein a control input of the delay unit is connected to an address unit configured to read a content in the memory unit and provide the memory unit content at the delay unit output based on a signal at the control input.

7. The interface apparatus of claim 1 , wherein the signal processor unit comprises a signal processor having a synchronization output, and configured to output a synchronization signal when a particular signal applied to an input thereof is detected.

8. The interface apparatus of claim 7 , further comprising a clock generator connected downstream of the synchronization output of the signal processor, wherein the clock generator is configured to produce a synchronized clock signal that is coupled to a clock signal input of the delay unit.

9. The interface apparatus of claim 8 , wherein the clock generator comprises a reference input for receiving a reference signal.

10. The interface apparatus of claim 1 , wherein the data symbols which are output by the signal processor unit form at least one logic state.

11. A method for data recovery and synchronization in a transmitter, comprising:

receiving an analog signal in the transmitter comprising a first component and a second component with data symbols coded therein;

converting the analog signal to a discrete-value signal comprising a first component and a second component with data symbols coded therein;

decoding the data symbols from the discrete-value signal;

storing the decoded data symbols in a memory unit in the transmitter; and

reading the stored data symbols from the memory unit with a time delay defined by a period between the storing and the reading, wherein the time delay is adjustable,

wherein storing the data symbols in a memory unit comprises:

producing a synchronization signal based on a particular coded data symbol in the analog signal;

producing a clock signal based on the synchronization signal; and

storing the decoded data symbol in the memory unit at a timing based on the clock signal.

12. The method of claim 11 , wherein decoding the coded data symbols comprises:

converting the discrete-value signal into a second signal, whose frequency is shifted when a coded data symbol changes;

detecting the frequency of the second signal; and

producing a decoded data symbol based on the detected frequency.

13. A transmitter circuit for a radio frequency transmission, comprising:

a baseband unit configured to generate and output an analog signal representing a sequence of coded symbols;

a digital interface circuit configured to receive the analog signal and convert the analog signal into a discrete-value signal representing the data symbols; and

a digital modulator configured to receive a local oscillator signal and the discrete-value signal and output a radio frequency transmission signal in accordance therewith,

wherein the digital interface circuit comprises:

an analog/digital converter configured to convert the analog signal into a digital signal;

a phase circuit configured to receive the digital signal and generate a phase signal in response thereto; and

a signal processor circuit configured to convert the phase signal into a signal that represents a frequency, and further configured to produce a sequence of symbols based on the frequency signal.

14. The transmitter of claim 13 , further comprising a delay circuit comprising a memory unit configured to receive the sequence of symbols from the signal processor at a first time and output the sequence of symbols at a second time, wherein a time delay between the first and second times is adjustable based on a control signal.