Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch
View Patent ↗A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the smallest L1 cache miss penalty supported by the memory subsystem. In response to a demand miss, a load/store unit sends a fetch request to the next level cache. The cache line of the demand miss is examined to identify the critical sector. Once the critical sector is identified, a best-case data return time is determined based on the fastest time the next level cache is able to return the critical sector of the cache line. The load/store unit then sends a speculative warning to the dispatch unit to coincide with the best-case data return, wherein the speculative warning prepares the dispatch unit to resend the instruction for execution as soon as data is available to the processor core.
1. A method in a data processing system for maintaining a best-case demand redispatch of an instruction, the method comprising:
responsive to a demand miss, sending a fetch request to a next level cache in a memory hierarchy;
examining a cache line of the demand miss to identify a critical sector of the cache line;
generating a best-case data return arrival time by determining a fastest time the next level cache is able to return the critical sector of the cache line; and
sending a speculative warning to a dispatch unit to coincide with the best-case data return arrival time, wherein the speculative warning prepares the dispatch unit to resend the instruction for execution as data in the next level cache becomes available to a processor core.
2. The method of claim 1 , wherein the speculative warning prepares the dispatch unit for a restart expected due to a data-coming signal from the next level cache.
3. The method of claim 2 , further comprising;
responsive to an indication that the data-coming signal is not valid, sending another speculative warning to the dispatch unit.
4. The method of claim 3 , wherein the data-coming signal is not valid due to a resource conflict and the next level cache cannot provide requested data.
5. The method of claim 2 , further comprising:
prior to receiving an indication that the data-coming signal is not valid, receiving one or more subsequent data-coming signals.
6. The method of claim 1 , wherein the critical sector is a subsection of the cache line containing data to be used by a demand load that fetched the cache line.
7. The method of claim 1 , wherein the sending, examining, and generating steps are performed by a load/store unit.
8. The method of claim 1 , wherein determining the fastest time the next level cache is able to return the cache line includes determining a longest allowable time delay upon which the speculative warning must be sent to the dispatch unit.
9. The method of claim 8 , wherein sending the speculative warning after the longest allowable time delay maximizes a time the dispatch unit operates in lookahead execution mode.