Differential analog logic circuit with symmetric inputs and output
A logic circuit incorporates symmetric inputs and/or a symmetric output. The logic circuit may include symmetric input circuits such that each input signal may be processed by a circuit that provides substantially identical rise times and fall times. The input circuits may provide symmetric loading of the input signals by providing a substantially identical circuit configuration for each input signal. The logic circuit may include a symmetric output circuit such that the output signals generated by the output circuit may have substantially identical rise times and fall times. Each leg of a differential output circuit may incorporate a substantially identical circuit configuration.
1 . A logic circuit comprising:
a first input circuit coupled to receive a first input signal;
a second input circuit coupled to receive a second input signal;
wherein the first input circuit and the second input circuit are configured to provide symmetric loading of the first input signal and the second input signal; and
an output circuit configured to generate an output signal;
wherein at least one of the first input circuit, the second input circuit and the output circuit is configured to generate rising and falling edges of signals using the same type of transistor.
2 . The logic circuit of claim 1 wherein the first input circuit and the second input circuit are configured to couple the same number of transistors to the first input signal and the second input signal, respectively.
3 . The logic circuit of claim 1 wherein the first input circuit and the second input circuit are configured to couple the same types of transistors to the first input signal and the second input signal, respectively.
4 . The logic circuit of claim 1 wherein the first input circuit and the second input circuit are configured to couple the first input signal and the second input signal, respectively, to substantially similar signal paths.
5 . The logic circuit of claim 1 wherein the logic circuit generates the rising and falling edges using NMOS transistors.
6 . The logic circuit of claim 1 comprising dummy circuits for loading the input signals.
7 . The logic circuit of claim 1 comprising dummy circuits for loading the output signals.
8 . The logic circuit of claim 1 wherein the logic circuit is configured to perform a least one of AND, NAND, OR, NOR and XOR logic operations.
9 . A method of performing a logic operation comprising:
receiving input signals;
providing symmetric loading for the input signals;
generating rising and falling edges of signals using the same type of transistors;
providing symmetric loading for output signals; and
providing the output signals.
10 . The method of claim 9 wherein the providing symmetric loading comprises coupling each input signal to the same number of components.
11 . The method of claim 9 wherein the providing symmetric loading comprises coupling each input signal to the same type of components.
12 . The method of claim 9 wherein the providing symmetric loading comprises providing substantially similar signal paths for each input signal.
13 . The method of claim 9 wherein the generating rising and falling edges of signals comprises using NMOS transistors.
14 . The method of claim 9 wherein the logic operation comprises AND, NAND, OR, NOR or XOR logic operations.
15 . A logic circuit comprising:
a first differential transistor pair coupled to a first input terminal to receive a first differential input signal and coupled to an output terminal to generate a differential output signal;
a second differential transistor pair coupled to a second input terminal to receive a second differential input signal and coupled to the output terminal to generate the differential output signal;
a third differential transistor pair coupled to the output terminal to generate the differential output signal;
a fourth differential transistor pair coupled to the output terminal to generate the differential output signal;
a first bias transistor coupled to receive a first leg of the second input signal and coupled to provide a first bias signal to the first differential pair;
a second bias transistor coupled to receive a first leg of the first input signal and coupled to provide a second bias signal to the second differential pair;
a third bias transistor coupled to receive a second leg of the second input signal and coupled to provide a third bias signal to the third differential pair; and
a fourth bias transistor coupled to receive a second leg of the first input signal and coupled to provide a fourth bias signal to the fourth differential pair.
16 . The logic circuit of claim 15 wherein inputs of the third differential pair are coupled to receive power supply signals.
17 . The logic circuit of claim 15 wherein inputs of the fourth differential pair are coupled to receive power supply signals.
18 . The logic circuit of claim 15 comprising a current source configured to provide the first bias signal, the second bias signal, the third bias signal and the fourth bias signal to the first bias transistor, the second bias transistor, the third bias transistor and the fourth bias transistor, respectively.
19 . The logic circuit of claim 15 wherein the logic circuit is configured to perform a least one of AND, NAND, OR, NOR and XOR logic operations.