Dynamic recalculation of resource vector at issue queue for steering of dependent instructions
View Patent ↗A method and apparatus for steering instructions dynamically, at issue time, so as to maximize the efficiency of use of execution units being shared by multiple threads being processed by an SMT processor. Resource vectors are used at issue time to redirect instructions, from threads being processed simultaneously, to shared resources for which the multiple threads are competing. The existing resource vectors for instructions that are queued for issuance are analyzed and, where appropriate, dynamically recalculated and modified for maximum efficiency.
1. A method of redirecting instructions of a plurality of threads in a processor, comprising:
identifying a statically-assigned execution unit assignment for each instruction;
issuing said instructions to a floating point issue queue;
analyzing the execution unit assignment for the issued instructions in each thread;
determining if the statically assigned execution unit assignments can be optimized by changing the statically assigned assignments; and
dynamically steering any of said issued instructions whose execution unit assignments can be optimized to new execution unit assignments that achieve optimization of said processor.
2. The method of claim 1 , wherein said dynamic steering is performed using said floating point issue queue.
3. The method of claim 2 , wherein:
said analyzing step comprises the analysis of resource vector bits for each instruction; and
said floating point issue queue dynamically recalculates and modifies the resource vector bits to steer the instructions to execution units so as to achieve said optimization.
4. The method of claim 3 , wherein said optimization is achieved by steering dependent instructions to the same execution unit as that of an instruction from which the dependent instruction depends.
5. The method of claim 3 , wherein said optimization is achieved by steering instructions around execution units that are busy.
6. The method of claim 3 , wherein said processor comprises an SMT processor.