Low-power signal chair for image sensors
View Patent ↗A signal chain for an image sensor is disclosed. The signal chain includes photo sensing elements, pixel readout circuits, and an amplifier. Each pixel readout circuit receives a charge-induced signal and a reset signal from one of the photo sensing elements. The readout circuit computes a difference signal between the charge-induced signal and said reset signal. The difference signal is measured with respect to a reference signal. The amplifier is coupled to the pixel readout circuits, and configured to supply the reference signal during computation of the difference signal. Further, the amplifier amplifies the difference signal when the computation is done.
1. An imaging apparatus, comprising:
a plurality of pixels, each for outputting at different times, a reset signal and a pixel signal;
a read out circuit comprising:
a sampling circuit comprising:
a column line for receiving said reset and pixel signals;
a first sampling capacitor, said first sampling capacitor having a first plate for receiving said reset and pixel signals from said column line and a second plate for outputting a first output signal based on a voltage difference of said reset and pixel signals; and
a first output line for receiving said first output signal; and
an amplifying circuit, configured to amplify said first output signal into a second output signal, said amplifying circuit comprising:
an amplifier having a first input coupled to said first output line and a second input coupled to a source of a reference voltage;
a feedback network, coupled between an output of said amplifier and said first input; and
a second output line, coupled in parallel to a first analog-to-digital converter and a second analog-to-digital converter.
2. The imaging apparatus of claim 1 , wherein said first and second analog-to-digital converters each comprise:
a comparator;
a sample capacitor, coupled to a first input of said comparator;
a binary-scaled capacitor network, coupled to a second input of said comparator; and
a plurality of latches, coupled an output of said comparator.
3. The imaging apparatus of claim 2 , wherein one of said first and second analog-to-digital converters is set into a first configuration for converting said second output signal in a particular cycle; and
another one of said first and second analog-to-digital converters is set into a second configuration for sampling a next second output signal; and
said first and second analog-to-digital converters are configured to switch configurations after said particular cycle.
4. The imaging apparatus of claim 1 , wherein said feedback network comprises:
a switch for coupling said output of said amplifier to said first input of said amplifier, thereby providing said reference voltage to said first sampling capacitor.
5. An imager, comprising:
a pixel array, comprising a plurality of pixels for producing reset and pixel signals, said pixel array being organized into a plurality of rows and a plurality of columns;
addressing circuits, coupled to said pixel array, configured to select an addressed row of pixels from said pixel array; and
a plurality of read out circuits, each respectively associated with one column of said selected row of pixels and comprising:
a sampling circuit comprising:
a column line for receiving said reset and pixel signals;
a first sampling capacitor, said first sampling capacitor having a first plate for receiving said reset and pixel signals from said column line and a second plate for providing a first output signal based on a voltage difference of said reset and pixel signals; and
a first output line for receiving said first output signal; and
an amplifying circuit, configured to amplify said first output signal into a second output signal, said amplifying circuit comprising:
an amplifier having a first input coupled to said first output line and a second input coupled to a source of a reference voltage;
a feedback network, coupled between an output of said amplifier and said first input; and
a second output line, coupled in parallel to a first analog-to-digital converter and a second analog-to-digital converter.
6. The imager of claim 5 , wherein said first and second analog-to-digital converters each comprise:
a comparator;
a sample capacitor, coupled to a first input of said comparator;
a binary-scaled capacitor network, coupled to a second input of said comparator; and
a plurality of latches, coupled an output of said comparator.
7. The imager of claim 6 , wherein one of said first and second analog-to-digital converters is set into a first configuration for converting said second output signal in a particular cycle; and
another one of said first and second analog-to-digital converters is set into a second configuration for sampling a next second output signal; and said first and second analog-to-digital converters are configured to switch configurations after said particular cycle.
8. The imager of claim 5 , wherein said feedback network comprises:
a switch for coupling said output of said amplifier to said first input of said amplifier, thereby providing said reference voltage to said first sampling capacitor.
9. The imaging apparatus of claim 1 , wherein said first sampling capacitor is configured to settle to a voltage difference between said photo and reset signals.
10. The imaging apparatus of claim 5 , wherein said first sampling capacitor is configured to settle to a voltage difference between said photo and reset signals.