Method and apparatus for an improved power amplifier
View Patent ↗A power amplifier assembly has a first power amplifier with a first input conditioning circuit. At least first and second amplifiers are in parallel with each other and having inputs and outputs. An input signal is coupled to the inputs of the first and second amplifiers. A first multi-input power combiner is provided. The outputs of the at least first and second parallel amplifiers are combined by the first multi-input power combiner to add signals of the outputs constructively. A second power amplifier has a first input conditioning circuit. At least first and second amplifiers are in parallel with each other and having inputs and outputs. An input signal is coupled to the inputs of the first and second amplifiers. A second multi-input power combiner is provided. The outputs of the at least first and second parallel amplifiers are combined by the second multi-input power combiner to add signals of the outputs constructively.
1. A power amplifier assembly, comprising:
a first power amplifier including,
a first input conditioning circuit,
at least first and second amplifiers in parallel with each other and having an input and an output, an input signal coupled to the inputs of the at least the first and second amplifiers, and
a first multi-input power combiner, wherein the outputs of the at least first and second parallel amplifiers are combined by the first multi-input power combiner to add signals of the outputs constructively; and
a second power amplifier including,
a second input conditioning circuit,
at least first and second amplifiers in parallel with each other and having an input and an output, an input signal coupled to the inputs of the at least the first and second amplifier,
a second multi-input power combiner, wherein the outputs of the at least first and second parallel amplifiers are combined by the second multi-input power combiner to add signals of the outputs constructively; and
wherein the assembly has multiple inputs and each of an input of the multiple inputs has an individual buffer that can be independently controlled.
2. The assembly of claim 1 , wherein each of the first and second power amplifiers operates high or low band at an upper frequency band and a lower frequency band.
3. The assembly of claim 1 , wherein the first power amplifier operates at high band, and the second power amplifier operates at low band at an upper frequency band and a lower frequency band.
4. The assembly of claim 1 , wherein the assembly has a single RF input and a single RF output.
5. The assembly of claim 1 , wherein at least one of the first and second assemblies is tunable.
6. The assembly of claim 1 , wherein at least one of, the first or second input conditioning circuits, the amplifiers, and the first and second multi-input power combiners is tunable.
7. The assembly of claim 1 , wherein at least one of, the first or second input conditioning circuits, the amplifiers, and the first and second multi-input power combiners is configured to operate over an upper frequency band and a lower frequency band.
8. The assembly of claim 1 , wherein at least one of, the first or second input conditioning circuits, the amplifiers, and the first and second multi-input power combiners is configured to operate over more than one band.
9. The assembly of claim 1 , further comprising:
at least a first buffer amplifier that loads cell phone transceivers with individual buffers for each band.
10. A power amplifier assembly, comprising:
an input conditioning circuit,
at least first and second amplifiers in parallel with each other and having
an input and an output, an input signal coupled to the inputs of the at least the first and second amplifiers, and
a multi-input power combiner, wherein the outputs of the at least first and second parallel amplifiers are combined by the first multi-input power combiner to add signals of the outputs constructively, wherein the assembly is configured to provide upper and lower frequency band operation;
a low-band buffer;
a high-band buffer; and
a signal band select switch.
11. The assembly of claim 10 , wherein the assembly has a single input and a single output.
12. The assembly of claim 10 , wherein the assembly is configured to provide simultaneous two band operation.
13. The assembly of claim 10 , further comprising:
an upper and lower frequency band tuning control member.
14. The assembly of 10 , wherein at least one of the input conditioning circuit or the multi-input output power combiner is tunable.
15. The assembly of claim 10 , wherein at least one of, the input conditioning circuit, the amplifiers, and the multi-input power combiners is tunable.
16. The assembly of claim 1 , wherein the at least one of, the input conditioning circuit, the amplifiers, and the multi-input power combiners is configured to operate over an upper frequency band and a lower frequency band.
17. The assembly of claim 1 , wherein the at least one of, the input conditioning circuit, the amplifiers, and the multi-input power combiners is configured to operate over more than one band.
18. The assembly of claim 1 , wherein the assembly has multiple inputs.
19. A power amplifier assembly, comprising:
a first power amplifier including,
a first input conditioning circuit,
at least first and second amplifiers in parallel with each other and having an input and an output, an input signal coupled to the inputs of the at least the first and second amplifiers, and
a first multi-input power combiner, wherein the outputs of the at least first and second parallel amplifiers are combined by the first multi-input power combiner to add signals of the outputs constructively; and
a second power amplifier including,
a second input conditioning circuit,
at least first and second amplifiers in parallel with each other and having an input and an output, an input signal coupled to the inputs of the at least the first and second amplifier,
a second multi-input power combiner, wherein the outputs of the at least first and second parallel amplifiers are combined by the second multi-input power combiner to add signals of the outputs constructively; and
wherein the assembly has multiple inputs and each of an input of the multiple inputs has an individual buffer that can be independently controlled.
20. The assembly of claim 10 , wherein at least one of the first and second amplifiers is configured to operate at two different frequencies.
21. The assembly of claim 10 , wherein at least one of the first and second amplifiers is broadband.
22. The assembly of claim 10 , wherein the assembly has a plurality of individual inputs and a single output.
23. A power amplifier assembly, comprising:
an input conditioning circuit,
at least first and second amplifiers in parallel with each other and having
an input and an output, an input signal coupled to the inputs of the at least the first and second amplifiers, and
a multi-input power combiner, wherein the outputs of the at least first and second parallel amplifiers are combined by the first multi-input power combiner to add signals of the outputs constructively, wherein the assembly is configured to provide upper and lower frequency band operation:
at least one of a series voltage regulation device, a PMOS transistor or a PNP transistor; and
an opamp configured to set an internal power supply voltage to a desired level pursuant to a analog control voltage.
24. The assembly of claim 23 , wherein the opamp is coupled in a voltage follower configuration where the internal power supply voltage across a last amplifier in a set of amplifiers is identical to the analog control voltage.
25. The assembly of claim 23 , wherein the opamp is coupled in a linear function configuration where the internal power supply voltage across a last amplifier in a set of amplifiers is a linear function of the analog control voltage.
26. The assembly of claim 23 , wherein the assembly provides a limiting function.
27. The assembly of claim 23 , wherein the series voltage regulation device is on or off chip when the assembly is a CMOS power amplifier assembly.
28. The assembly of claim 23 , wherein the series voltage regulation device has a cascode connected series voltage regulation device.
29. The assembly of claim 23 , wherein a drive level to an input to the series voltage regulation device is limited to provide that no damage to the series voltage regulation device occurs in response to breakdown.
30. The assembly of claim 28 , wherein the cascode connected series voltage regulation device is on or off chip.
31. The assembly of claim 26 , wherein breakdown limits of drain source terminals of the cascode connected series voltage regulation device is reduced.
32. The assembly of claim 23 , further comprising:
at least a second series voltage regulation device.
33. The assembly of claim 32 , wherein a gate source voltage applied to the series voltage regulation devices is limited.
34. The assembly of claim 8 , further comprising:
a first set of amplifiers that includes the first amplifier; and
a second set of amplifiers that includes the second amplifier.
35. The assembly of claim 34 , wherein internal power supply voltage of at least one of an amplifier in the first and second sets of amplifiers is controlled.
36. The assembly of claim 34 , wherein power of at least one amplifier in the first and second sets of amplifiers is lower than other amplifiers in its respective set of first and second sets of amplifiers.
37. The assembly of claim 34 , wherein power of at least one of a last amplifier in the first and second sets of amplifiers is lower than other amplifiers in the respective first and second sets of amplifiers.
38. The assembly of claim 37 , further comprising:
at least one non-linear transfer function element configured to take its input from the internal power supply voltage of a last amplifier in the first and second sets of amplifiers.
39. The assembly of claim 38 , wherein analog control voltage is the input from the internal power supply voltage.
40. The assembly of claim 34 , further comprising:
at least one attenuator coupled to at least one input of an amplifier in the first and second sets of amplifiers.
41. The assembly of claim 31 , wherein a control input for the attenuator is non-linear and derived from an output from a non-linear transfer function element.
42. The assembly of claim 32 , wherein the attenuator is adjustable simultaneously in conjunction with adjustments to at least one of the first and second amplifiers in the first and second amplifier sets.