Method of manufacturing thin film transistor, method of manufacturing electro-optical device thin film transistor, and electro-optical device
View Patent ↗A method of manufacturing a transistor includes the step of forming on a substrate a source electrode and drain electrode by selective electroless plating after patterning a charge control agent attached to the substrate using light, and the step of forming an organic semiconductor, a gate insulation layer, and a gate electrode.
1. A method of manufacturing a transistor, comprising:
forming a source electrode and a drain electrode over a substrate by an electroless plating method, the source electrode having a thickness in the range of 30 nm to 300 nm;
forming an organic semiconductor layer over the source electrode and the drain electrode;
forming an insulating layer over the semiconductor layer; and
forming a gate electrode over the insulating layer, wherein the electroless plating method includes:
attaching charge control agents to a first region of the substrate, each of the charge control agents being a cationic surfactant;
irradiating a first part of the first region with a light using a photomask to remove a part of the charge control agents on the first part of the first region;
attaching at least one of a catalytic agent and a precursor of the catalytic agent to a second part of the first region, which is different from the first part of the first region; and
depositing a metallic layer from a metal salt solution on the second part of the first region attached with one of the catalytic agent and the precursor of the catalytic agent to form the source electrode and the drain electrode.
2. The method of manufacturing a transistor according to claim 1 , wherein a channel length between the source electrode and the drain electrode is in the range of 5 μm to 20 μm.
3. The method of manufacturing a transistor according to claim 1 , wherein a channel width between the source electrode and the drain electrode is in the range of 0.05 mm to 5 mm.
4. The method of manufacturing a transistor according to claim 1 , wherein a channel width between the source electrode and the drain electrode is in the range of 0.1 mm to 2 mm.
5. The method of manufacturing a transistor according to claim 1 , wherein the thickness of the source electrode is in the range of 50 nm to 150 nm.
6. The method of manufacturing a transistor according to claim 1 , wherein the source electrode includes at least one of Pt, Pd, Ni, Cu, and Au.
7. The method of manufacturing a transistor according to claim 6 , wherein the organic semiconductor material includes including a conjugated polymer.
8. The method of manufacturing a transistor according to claim 1 , wherein the substrate is a polyimide substrate.
9. The method of manufacturing a transistor according to claim 1 , wherein the electroless plating method uses a plating solution that is not including alkali ion.