Apparatus and method for interfacing with a high speed bi-directional network
View Patent ↗A method and apparatus for processing a bi-directional dataflow are disclosed which permits the transparent movement of data from one processor to another via a shared memory fabric which is connected with both processors. This permits the incoming data of a first processor to be utilized by a second processor thereby freeing that processor from having to handle incoming data. Further, the second processor can handle outgoing data exclusively, freeing the first processor from having to handle outgoing data. In this way, each direction of a bi-directional dataflow may be handled by the maximum capability of a bi-directional capable processing device. The shared memory may comprise a plurality of banks of synchronous dynamic random access memory (SDRAM) devices, and may be used to store packet data in a network.
1. A method of processing data in a bi-directional processing device, the method comprising:
(a) receiving said data by a first processor from a bi-directional interface, said first processor operative to perform a first task on said data thereby resulting in processed data;
(b) accessing a shared memory by said first processor to store said processed data in a the shared memory;
(c) accessing said shared memory by a second processor to retrieve said processed data from said shared memory to perform a second task on said processed data thereby resulting in secondarily processed data, the accessing of said shared memory by said second processor not being based on an indication from said first processor; and
(d) transmitting, selectively, said secondarily processed data to said hi-directional interface from said second processor.
2. The method of claim 1 , wherein said first task comprises at least one of inspection and analysis.
3. The method of claim 1 , wherein said second task comprises taking an action on said processed data.
4. The method claim 3 , wherein said taking an action comprises at least one of deleting, modifying and transmitting said processed data.
5. The method of claim 1 , wherein each of said first and second processors is characterized by a hi-directional bandwidth, said method further comprising utilizing said bi-directional bandwidth for uni-directional data flow.
6. The method of claim 1 , wherein said storing further comprises storing said processed data such that said second processor is unaware of how said processed data was stored in said shared memory.
7. The method of claim 1 , wherein first and second processors comprise network processors.
8. The method of claim 1 , wherein said transmitting is further based on a result of said second task.
9. A bi-directional data processor comprising:
a first processor coupled with a bi-directional interface and operative to receive data from said bi-directional interface and perform a first task on said data thereby resulting in processed data;
a shared memory coupled with said first processor, wherein said first processor is further operative to access said shared memory to store said processed data in said shared memory; and
a second processor coupled with said shared memory and said bi-directional interface, said second processor operative to access said shared memory to retrieve said stored processed data from said shared memory, perform a second task on said stored processed data thereby resulting in secondarily processed data and selectively transmit said secondarily processed data back to said bi-directional interface, the accessing of said shared memory by said second processor not being based on an indication from said first processor.
10. The bi-directional data processor of claim 9 , wherein said first task comprises at least one of inspection and analysis.
11. The bi-directional data processor of claim 9 , wherein said second task comprises taking an action on said stored processed data.
12. The bi-directional data processor claim 11 , wherein said taking an action comprises at least one of deleting, modifying and transmitting said processed data.
13. The bi-directional data processor of claim 9 , wherein each of said first and second processors are characterized by a bi-directional bandwidth, said bi-directional bandwidth being utilized for uni-directional data flow.
14. The bi-directional data processor of claim 9 , wherein said second processor is unaware of how said processed data was stored in said shared memory.
15. The bi-directional data processor of claim 9 , wherein said first and second processors comprise network processors.
16. The bi-directional data processor of claim 9 , wherein said the selective transmission by said second processor is further based on a result of said second task.
17. An apparatus for processing a bi-directional dataflow comprising:
first processor means for receiving data from a bi-directional interface and performing a first task on said data thereby resulting in processed data;
shared memory means coupled with said first processor, wherein said first processor is further operative to access said shared memory means to store said processed data in said shared memory means; and
second processor means coupled with said shared memory and operative to access said shared memory means to retrieve said stored processed data from said shared memory, perform a second task on said processed data thereby resulting in secondly processed data and selectively transmit said data back to said bi-directional interface, the accessing of said shared memory means by said second processor means not being based on an indication from said first processor means.