IP Library Granted Patent US 7,908,419
Granted Patent B2
US 7,908,419 · App. 11/062,954 · Granted Mar 15, 2011

Data transfer control device and electronic instrument

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Quick Facts
Patent No.
US 7,908,419
App. No.
11/062,954
Granted
Mar 15, 2011
Kind
B2
Abstract

A data transfer control device includes: a link controller which analyzes a packet received from a host-side data transfer control device through a serial bus; and an interface circuit which generates interface signals and outputs the generated interface signals to an interface bus. A packet transferred from the host-side data transfer control device through the serial bus includes a synchronization signal code field for setting a synchronization signal code. The interface circuit generates synchronization signals FPFRAME and FPLINE included in the interface signals based on the synchronization signal code set in the packet.

Claims (30)

1. A data transfer control device that controls data transfer, the data transfer control device comprising:

a link controller that analyzes a packet received from a host-side data transfer control device through a serial bus; and

an interface circuit which generates interface signals and outputs the generated interface signals to an interface bus,

a packet transferred from the host-side data transfer control device through the serial bus including a synchronization signal code field for setting a synchronization signal code, the synchronization signal code including a plurality of data bits, a first one of the plurality of data bits being set to indicate that a horizontal synchronization signal is active, and a second one of the plurality of data bits being set to indicate that a vertical synchronization signal is active, and

the interface circuit generating the horizontal synchronization signal based on whether the first one of the plurality of data bits is set and the vertical synchronization signal based on whether the second one of the plurality of data bits is set.

2. The data transfer control device as defined in claim 1 ,

the link controller receiving a display period packet in which data is set in a data field from the host-side data transfer control device in a display period, and receives a non-display period packet in which data is not set in the data field from the host-side data transfer control device in a non-display period.

3. The data transfer control device as defined in claim 1 ,

upon receiving a display period packet in which data is set in a data field from the host-side data transfer control device, the link controller outputting a header including the synchronization signal code set in the packet and the data set in the packet to the interface circuit, and, upon receiving a non-display period packet in which data is not set in the data field from the host-side data transfer control device, the link controller outputting a header including the synchronization signal code set in the packet to the interface circuit.

4. The data transfer control device as defined in claim 2 ,

upon receiving the display period packet in which data is set in the data field from the host-side data transfer control device, the link controller outputting a header including the synchronization signal code set in the packet and the data set in the packet to the interface circuit, and, upon receiving the non-display period packet in which data is not set in the data field from the host-side data transfer control device, the link controller outputting a header including the synchronization signal code set in the packet to the interface circuit.

5. An electronic instrument, comprising:

data transfer control device as defined in claim 1 ;

the data transfer control device being a target-side data transfer control device;

a host-side data transfer control device connected with the target-side data transfer control device through the serial bus; and

one or more devices connected with the target-side data transfer control device through the interface bus.

6. An electronic instrument, comprising:

the data transfer control device as defined in claim 2 ;

the data transfer control device being a target-side data transfer control device; a host-side data transfer control device connected with the target-side data transfer control device through the serial bus; and

one or more devices connected with the target-side data transfer control device through the interface bus.

7. An electronic instrument, comprising:

the data transfer control device as defined in claim 3 ;

the data transfer control device being a target-side data transfer control device;

a host-side data transfer control device connected with the target-side data transfer control device through the serial bus; and

one or more devices connected with the target-side data transfer control device through the interface bus.

8. An electronic instrument, comprising:

the data transfer control device as defined in claim 4 ;

the data transfer control device being a target-side data transfer control device;

a host-side data transfer control device connected with the target-side data transfer control device through the serial bus; and

one or more devices connected with the target-side data transfer control device through the interface bus.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2020
From: SEIKO EPSON CORPORATION
To: 138 EAST LCD ADVANCEMENTS LIMITED
Reel/Frame 051707/0399 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2005
From: HONDA, HIROYASU
To: SEIKO EPSON CORPORATION
Reel/Frame 016338/0132 →