Semiconductor nonvolatile memory cell array
View Patent ↗A semiconductor nonvolatile memory cell array includes a plurality of semiconductor nonvolatile memory cells. Each memory cell has a control electrode ( 30 ); a pair of impurity diffusion regions ( 21, 22 ) to provide first and second main electrodes; a pair of variable resistance sections ( 24, 26 ); and a pair of charge storage sections ( 50, 52 ). The array has a word line ( 33 ) electrically connected to the control electrodes of the semiconductor nonvolatile memory cells and bit lines provided perpendicular to the word line and composed of the impurity diffusion regions; and layer insulation layers ( 57, 58 ) provided between the charge storage sections and the word line.
1. A semiconductor nonvolatile memory cell array comprising:
a plurality of semiconductor nonvolatile memory cells, each including:
a semiconductor substrate of a first conductive type;
a control electrode provided on said semiconductor substrate via an insulation layer;
a pair of impurity diffusion regions of a second conductive type provided on said semiconductor substrate on opposite sides of said control electrode to provide first and second main electrodes;
a channel region provided on said semiconductor substrate below said control electrode at a time of transistor operation;
a pair of variable resistance sections of a second conductive type provided between said channel region and said impurity diffusion regions, respectively, and having an impurity density lower than that of said impurity diffusion regions; and
a pair of charge storage sections provided one on each of said variable resistance sections;
at least one word line electrically connected to said control electrodes of said semiconductor nonvolatile memory cells;
at least one bit line provided perpendicular to said word line and composed of said impurity diffusion regions; and
at least one layer insulation layer provided between said charge storage sections and said word line.
2. The semiconductor nonvolatile memory cell array according to claim 1 , wherein a top surface of said control electrode and a top surface of said layer insulation layer constitute a continuous plane on which said word line is provided.
3. The semiconductor nonvolatile memory cell array according to claim 1 , wherein said impurity diffusion regions each include a salicide region.
4. The semiconductor nonvolatile memory cell array according to claim 1 , which further comprises a pair of side wall spacers provided one on each of said charge storage sections on said variable resistance sections.
5. The semiconductor nonvolatile memory cell array according to claim 4 , wherein said variable resistance sections each are composed of a low density diffusion variable resistance section extending from said channel region toward said impurity diffusion region and a high density diffusion variable resistance section having an impurity density higher than that of said low density diffusion variable resistance section and
said side wall spacers each are composed of a first side wall spacer provided on said low density diffusion variable resistance section and a second side wall spacer provided on said high density diffusion variable resistance section.
6. A semiconductor nonvolatile memory cell array comprising
a plurality of semiconductor nonvolatile memory cells, each including:
a semiconductor substrate of a first conductive type;
a control electrode provided on said semiconductor substrate via an insulation layer;
a pair of impurity diffusion regions of a second conductive type provided on said semiconductor substrate on opposite sides of said control electrode to provide first and second main electrodes;
a channel region provided on said semiconductor substrate below said control electrode at a time of transistor operation;
a pair of variable resistance sections of a second conductive type provided between said channel region and said impurity diffusion regions, respectively, and having an impurity density lower than that of said impurity diffusion regions; and
a pair of charge storage sections provided one on each of said variable resistance sections;
at least one word line electrically connected to said control electrodes of said semiconductor nonvolatile memory cells;
at least one bit line provided perpendicular to said word line and composed of said impurity diffusion regions;
a pair of side wall spacers provided one on each of said variable resistance sections; and
at least one oxide layer provided on each of said impurity diffusion regions, wherein
said word line is provided in contact with a top surface of said control electrode and a top surface of said oxide layer.